Low ohmic layout technique for MOS transistors

  • US 20050250300A1
  • Filed: 05/07/2004
  • Published: 11/10/2005
  • Est. Priority Date: 05/07/2004
  • Status: Active Grant
First Claim
Patent Images

1. A circuit, comprising:

  • (a) a plurality of transistors, each with source and drain regions formed in a substrate;

    (b) a first interconnect layer formed on top of said substrate;

    (c) a second interconnect layer formed on top of said substrate;

    (d) a first plurality of contacts connecting said source regions to one of said first or second interconnect layers; and

    (e) a second plurality of contacts connecting said drain regions to the other of said first or second interconnect layers;

    wherein said first interconnect layer occupies a region above said substrate area in which the plurality of transistors reside, and wherein said second interconnect layer is located above said plurality of transistors and has openings therein for one of said respective first or second plurality of contacts to pass therethrough and couple to said at least one first interconnect layer.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×