Apparatus and methods for adjusting performance of programmable logic devices

• US 20050258862A1
• Filed: 05/19/2004
• Published: 11/24/2005
• Est. Priority Date: 05/19/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Rahim, Irfan, Pedersen, Bruce, Liu, Yow-Juang W., McElheny, Peter
• Granted Patent: US 7,348,827 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/00369 Modifications for compensating variations of temperature, supply voltage or other physical parameters
• CPC Class Codes: H03K 19/1731 Optimisation thereof
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Claims

1. A programmable logic device (PLD), comprising a body-bias generator configured to set a body bias of a transistor within the programmable logic device, wherein the body-bias generator sets the body bias of the transistor so as to trade off performance and power consumption of the transistor.

2. The programmable logic device (PLD) according to claim 1, wherein the transistor comprises a metal oxide semiconductor (MOS) transistor.

3. The programmable logic device (PLD) according to claim 1, wherein the transistor comprises a partially depleted silicon-on-insulator (SOI) transistor.

4. The programmable logic device (PLD) according to claim 1, wherein the body-bias generator is further configured in response to programmable logic device configuration data.

5. The programmable logic device (PLD) according to claim 1, wherein the body-bias generator is further configured to set the body bias of the transistor by adjusting a voltage applied between a source of the transistor and a body of the transistor.

6. The programmable logic device (PLD) according to claim 5, wherein the body-bias generator is further configured to adjust the voltage applied between a source of the transistor and the body of the transistor in response to information received from an information source external to the programmable logic device (PLD).

7. The programmable logic device (PLD) according to claim 5, wherein the body-bias generator is further configured to adjust the voltage applied between a source of the transistor and the body of the transistor in response to a temperature level of a circuit in the programmable logic device (PLD).

8. The programmable logic device (PLD) according to claim 1, wherein the transistor resides within a programmable logic circuit within the programmable logic device (PLD).

9. The programmable logic device (PLD) according to claim 8, wherein the programmable logic circuit comprises one of a plurality of programmable logic circuits arranged as a two-dimensional array within the programmable logic device (PLD).

10. The programmable logic device (PLD) according to claim 9, wherein the programmable logic circuit comprises a logic element.

11. The programmable logic device (PLD) according to claim 10, wherein the programmable logic circuit comprises local interconnect circuitry.

12. The programmable logic device (PLD) according to claim 1, wherein the transistor resides within a programmable interconnect circuit within the programmable logic device (PLD).

13. The programmable logic device (PLD) according to claim 8, wherein the programmable interconnect circuitry comprises local interconnect circuitry within a programmable logic circuit.

14. The programmable logic device (PLD) according to claim 1, wherein the transistor resides in a multiplexer (MUX).

15. The programmable logic device (PLD) according to claim 1, wherein the transistor resides in an input/output (I/O) circuitry.

16. The programmable logic device (PLD) according to claim 1, wherein the transistor resides in a processor within the programmable logic device (PLD).

17. The programmable logic device (PLD) according to claim 1, wherein the transistor resides in a control circuitry.

18. The programmable logic device (PLD) according to claim 1, wherein the transistor resides in a memory circuitry.

19. A programmable logic device (PLD), comprising:

a control circuitry;

a body-bias generator coupled to the control circuitry, the body-bias generator configured to set a body bias of a transistor within the programmable logic device (PLD); and

a variable impedance device coupled to the control circuitry, the variable impedance device configured to control power dissipation of a first circuit within the programmable logic device (PLD).

20. The programmable logic device (PLD) according to claim 19, wherein the first circuit comprises a circuit unused in an electronic circuit implemented by the programmable logic device (PLD).

21. The programmable logic device (PLD) according to claim 20, wherein the variable impedance device comprises a field-effect transistor (FET).

22. The programmable logic device (PLD) according to claim 21, wherein the body-bias generator is configured to set the body bias of the transistor so as to avoid thermal runaway within the programmable logic device (PLD).

23. The programmable logic device (PLD) according to claim 21, wherein the body-bias generator is further configured to adjust the body bias of the transistor so as to trade off performance and power consumption of the transistor.

24. The programmable logic device (PLD) according to claim 23, wherein the body-bias generator is further configured to adjust the body bias of the transistor so as to optimize the tradeoff between the performance and power consumption of the transistor.

25. The programmable logic device (PLD) according to claim 19, wherein the variable impedance device is further configured to shut down the first circuit by interrupting a supply of power to the first circuit.

26. The programmable logic device (PLD) according to claim 25, wherein the supply of power to the first circuit is provided by a supply-voltage circuit within the programmable logic device (PLD).

27. A programmable logic device (PLD), comprising:

a temperature sensor, the temperature sensor configured to sense a temperature of a first circuit in the programmable logic device (PLD);

a body-bias generator configured to set a body bias of a set of transistors in response to a control signal; and

a control circuit coupled to the temperature sensor and the body-bias generator, the control circuit configured to provide the control signal in response to a signal received from the temperature sensor.

28. The programmable logic device (PLD) according to claim 27, wherein the control circuit is further configured to provide the control signal so as to avoid thermal runaway in the set of transistors.

29. The programmable logic device (PLD) according to claim 27, wherein the control circuit is further configured to provide the control signal so as to trade off performance and power consumption of the set of transistors.

30. The programmable logic device (PLD) according to claim 29, wherein the control circuit is further configured to provide the control signal so as to optimize the tradeoff between the performance and power consumption of the set of transistors.

31. The programmable logic device (PLD) according to claim 27, wherein the set of transistors resides in the first circuit.

32. The programmable logic device (PLD) according to claim 27, wherein the control circuit is further configured to derive the control signal from a reference signal and a signal received from the temperature sensor.

33. A programmable logic device (PLD), comprising:

means for deriving a body-bias signal from at least one parameter related to the programmable logic device (PLD); and

means for providing the body-bias signal to a transistor in a first circuit within the programmable logic device (PLD) in response to an input signal.

34. The programmable logic device (PLD) according to claim 33, wherein the at least one parameter comprises a temperature level.

35. The programmable logic device (PLD) according to claim 34, wherein the temperature level comprises an operating temperature of the first circuit.

36. The programmable logic device (PLD) according to claim 33, wherein the at least one parameter comprises a performance characteristic of the first circuit.

37. The programmable logic device (PLD) according to claim 33, wherein the at least one parameter comprises a performance characteristic of the first circuit and a temperature level.

38. The programmable logic device (PLD) according to claim 37, wherein the temperature level comprises an operating temperature of the first circuit.

39. The programmable logic device (PLD) according to claim 33, wherein the at least one parameter comprises control information provided by a source external to the programmable logic device (PLD).

40. The programmable logic device (PLD) according to claim 33, wherein the input signal is provided by a configuration memory (CRAM).

41. The programmable logic device (PLD) according to claim 33, wherein the first circuit comprises programmable logic.

42. The programmable logic device (PLD) according to claim 33, wherein the first circuit comprises programmable interconnect.

43. The programmable logic device (PLD) according to claim 33, wherein the first circuit comprises a processor.

44. The programmable logic device (PLD) according to claim 33, wherein the first circuit comprises a controller.

45. The programmable logic device (PLD) according to claim 33, wherein the first circuit comprises input/output (I/O) circuitry.

46. A method of configuring a programmable logic device (PLD) to implement an electronic circuit, the method comprising:

mapping the electronic circuit to functional resources within the programmable logic device (PLD) to generate a design to be implemented by the programmable logic device (PLD);

identifying at least one critical circuit path in the design to be implemented by the programmable logic device (PLD); and

programming a body-bias level of at least one transistor in the at least one critical circuit path.

47. The method according to claim 46, wherein programming a body-bias level of the at least one transistor further comprises programming a configuration memory (CRAM) of the programmable logic device (PLD).

48. The method according to claim 47, wherein programming a body-bias level of the at least one transistor further comprises adjusting a voltage between a source and a body of the at least one transistor depending on a value programmed in the configuration memory (CRAM).

49. The method according to claim 46, further comprising disabling unused functional resources within the programmable logic device (PLD).

50. The method according to claim 46, further comprising controlling power dissipation of a first circuit within the programmable logic device (PLD).

51. The method according to claim 46, wherein programming a body-bias level of at least one transistor further comprises setting the body-bias level so as to avoid thermal runaway in the at least one transistor.

52. The method according to claim 46, wherein programming a body-bias level of at least one transistor further comprises setting the body-bias level so as to trade off performance and power consumption of the at least one transistor.

53. The method according to claim 52, wherein setting the body-bias level so as to trade off performance and power consumption of the at least one transistor further comprises optimizing the tradeoff between the performance and power consumption of the at least one transistor.

54. A method of operating a programmable logic device (PLD), the method comprising:

setting a body-bias level of at least one transistor in the programmable logic device (PLD) to a first level;

determining whether a performance measure of the programmable logic device (PLD) meets a criterion; and

adjusting the body-bias level of the at least one transistor depending on whether the performance measure of the programmable logic device (PLD) meets the criterion.

55. The method according to claim 54, wherein determining whether a performance measure of the programmable logic device (PLD) meets a criterion further comprises obtaining the performance measure.

56. The method according to claim 55, wherein adjusting the body-bias level of the at least one transistor further comprises:

leaving the body-bias level of the at least one transistor unchanged if the performance measure of the programmable logic device (PLD) meets the criterion; and

changing the body-bias level of the at least one transistor to a second level if the performance measure of the programmable logic device (PLD) fails to meet the criterion.

57. The method according to claim 56, wherein the performance measure comprises a speed of operation of the at least one transistor.

58. The method according to claim 56, wherein the performance measure comprises a power consumption of the at least one transistor.

59. The method according to claim 56, wherein the performance measure comprises a result of a self-test of the programmable logic device (PLD).

60. The method according to claim 58, further comprising disabling unused circuitry within the programmable logic device (PLD).

61. The method according to claim 58, further comprising controlling power dissipation of a first circuit within the programmable logic device (PLD).

62. A method of operating a programmable logic device (PLD), the method comprising:

setting a body-bias level of at least one transistor in the programmable logic device (PLD) to a first level;

determining whether a performance measure and a temperature level of the programmable logic device (PLD) meet at least one criterion;

adjusting the body-bias level of the at least one transistor depending on whether the performance measure and the temperature level of the programmable logic device (PLD) meet the criterion.

63. The method according to claim 62, determining whether a performance measure and a temperature level of the programmable logic device (PLD) meet at least one criterion further comprises:

obtaining the performance measure; and

obtaining the temperature level.

64. The method according to claim 63, wherein adjusting the body-bias level of the at least one transistor further comprises:

leaving the body-bias level of the at least one transistor unchanged if the performance measure and the temperature level of the programmable logic device (PLD) meet the at least one criterion; and

changing the body-bias level of the at least one transistor to a second level if the performance measure and the temperature level of the programmable logic device (PLD) fail to meet the at least one criterion.

65. The method according to claim 64, wherein the performance measure comprises a speed of operation of the at least one transistor.

66. The method according to claim 64, wherein the performance measure comprises a power consumption of the at least one transistor.

67. The method according to claim 66, further comprising disabling unused circuitry within the programmable logic device (PLD).

68. The method according to claim 66, further comprising controlling power dissipation of a first circuit within the programmable logic device (PLD).

69. A method of operating a programmable logic device (PLD) configured to function in an operating environment, the method comprising:

setting a body-bias level of at least one transistor in the programmable logic device (PLD) to a first level; and

adjusting the body-bias level of the at least one transistor depending on at least one characteristic of the operating environment of the programmable logic device (PLD).

70. The method according to claim 69, wherein adjusting the body-bias level of the at least one transistor further comprises adjusting the body-bias level of the at least one transistor to a second level if the at least one characteristic of the operating environment indicates that a performance of the at least one transistor should be changed.

71. The method according to claim 70, wherein adjusting the body-bias level of the at least one transistor further comprises increasing an operating speed of the at least one transistor if the at least one characteristic of the operating environment indicates that a performance of the at least one transistor should be increased.

72. The method according to claim 71, wherein adjusting the body-bias level of the at least one transistor further comprises trading off the operating speed of the transistor with a power consumption of the transistor.

73. The method according to claim 71, wherein adjusting the body-bias level of the at least one transistor further comprises selecting the second level so as to avoid thermal runaway of the at least one transistor.

74. The method according to claim 70, wherein adjusting the body-bias level of the at least one transistor further comprises decreasing an operating speed of the at least one transistor if the at least one characteristic of the operating environment indicates that a performance of the at least one transistor should be decreased.

75. The method according to claim 70, further comprising disabling unused circuitry within the programmable logic device (PLD).

76. The method according to claim 70, further comprising controlling power dissipation of a first circuit within the programmable logic device (PLD).

77. A method of operating a programmable logic device (PLD) configured to function in an operating environment, the method comprising:

setting a body-bias level of at least one transistor in the programmable logic device (PLD) to a first level; and

adjusting the body-bias level of the at least one transistor depending on at least one characteristic of the operating environment and a temperature level of the programmable logic device (PLD).

78. The method according to claim 77, wherein adjusting the body-bias level of the at least one transistor further comprises adjusting the body-bias level of the at least one transistor to a second level if the at least one characteristic of the operating environment and the temperature level indicate that a performance of the at least one transistor should be changed.

79. The method according to claim 78, further comprising disabling unused circuitry within the programmable logic device (PLD).

80. The method according to claim 78, further comprising controlling power dissipation of a first circuit within the programmable logic device (PLD).