Multistandard video decoder

• US 20050259688A1
• Filed: 12/01/2004
• Published: 11/24/2005
• Est. Priority Date: 05/21/2004
• Status: Active Grant

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gordon, Stephen
• Granted Patent: US 7,590,059 B2
• Time in Patent Office: Days
• US Class Current: 370/477
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 19/82 involving filtering within a prediction loop
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/44008 involving operations for analysing video streams, e.g. detecting features or characteristics in the video stream arrangements characterised by components specially adapted for monitoring, identification or recognition of video in broadcast systems H04H60/59

Abstract

Methods and systems for processing an encoded video stream are disclosed herein. Aspects of the method may comprise receiving on a chip, packetized data within the encoded video stream. An identifier within the received packetized data may be determined on the chip, where the identifier may define one of a plurality of encoding types associated with packets in the encoded video stream. A decoding process may be selected on the chip from a plurality of decoding processes, based on the determined identifier. A portion of the received packetized data in the encoded video stream may be decoded on the chip utilizing the selected decoding process. A header may be determined within the received packetized data that separates packets within the encoded video stream. A plurality of bytes within the received packetized data may be matched with a determined byte sequence.

Claims

1. A method for processing an encoded video stream, the method comprising:

receiving on a chip, packetized data within the encoded video stream;

determining on said chip, an identifier within said received packetized data that defines one of a plurality of encoding types associated with packets in the encoded video stream;

selecting on said chip, a decoding process from a plurality of decoding processes based on said determined identifier; and

decoding on said chip, at least a portion of said received packetized data in the encoded video stream utilizing said selected decoding process.

2. The method according to claim 1, further comprising determining on said chip, a start code within said received packetized data that separates packets within the encoded video stream.

3. The method according to claim 2, further comprising matching a plurality of bytes within said received packetized data with a determined byte sequence.

4. The method according to claim 3, further comprising removing said plurality of bytes from said received packetized data, if said plurality of bytes matches said determined byte sequence.

5. The method according to claim 1, further comprising decoding said at least a portion of said received packetized data utilizing at least one of a fixed length coding (FLC) process, a variable length coding (VLC) process and a context adaptive binary arithmetic coding (CABAC) process, if said determined identifier corresponds to H.264 video encoding.

6. The method according to claim 1, further comprising decoding said at least a portion of said received packetized data utilizing at least one of a FLC process and a VLC process, if said determined identifier corresponds to VC-1 video encoding.

7. The method according to claim 1, further comprising decoding said at least a portion of said received packetized data utilizing at least one of a FLC process and a VLC process, if said determined identifier corresponds to at least one of an H.261, H.263, H.263+, MPEG-1, MPEG-2 and MPEG-4 video encoding.

8. The method according to claim 1, wherein said decoded packetized data comprises at least one of prediction pixels information and prediction error information.

9. The method according to claim 1, further comprising generating a decoded video stream utilizing at least a portion of said decoded packetized data.

10. The method according to claim 1, further comprising, for each of said plurality of decoding processes, decoding on said chip said at least a portion of said received packetized data utilizing at least one of inverse transformation, inverse quantization, and motion compensation.

19. The machine-readable storage according to claim 11, further comprising code for generating a decoded video stream utilizing at least a portion of said decoded packetized data.

20. The machine-readable storage according to claim 19, further comprising code for filtering said generated decoded video stream utilizing at least one of an overlapped transform process and a deblocking process.

11. A machine-readable storage having stored thereon, a computer program having at least one code section for processing an encoded video stream, the at least one code section being executable by a machine to perform steps comprising:

receiving on a chip, packetized data within the encoded video stream;

determining on said chip, an identifier within said received packetized data that defines one of a plurality of encoding types associated with packets in the encoded video stream;

selecting on said chip, a decoding process from a plurality of decoding processes based on said determined identifier; and

decoding on said chip, at least a portion of said received packetized data in the encoded video stream utilizing said selected decoding process.

12. The machine-readable storage according to claim 11, further comprising code for determining on said chip, a start code within said received packetized data that separates packets within the encoded video stream.

13. The machine-readable storage according to claim 12, further comprising code for matching a plurality of bytes within said received packetized data with a determined byte sequence.

14. The machine-readable storage according to claim 13, further comprising code for removing said plurality of bytes from said received packetized data, if said plurality of bytes matches said determined byte sequence.

15. The machine-readable storage according to claim 11, further comprising code for decoding said at least a portion of said received packetized data utilizing at least one of a fixed length coding (FLC) process, a variable length coding (VLC) process and a context adaptive binary arithmetic coding (CABAC) process, if said determined identifier corresponds to H.264 video encoding.

16. The machine-readable storage according to claim 11, further comprising code for decoding said at least a portion of said received packetized data utilizing at least one of a FLC process and/or a VLC process, if said determined identifier corresponds to VC-1 video encoding.

17. The machine-readable storage according to claim 11, further comprising code for decoding said at least a portion of said received packetized data utilizing at least one of a FLC process and a VLC process, if said determined identifier corresponds to at least one of H.261, H.263, H.263+, MPEG-1, MPEG-2 and MPEG-4 video encoding.

18. The machine-readable storage according to claim 11, wherein said decoded packetized data comprises at least one of prediction pixels information and prediction error information.

21. A system for processing an encoded video stream, the system comprising:

at least one processor that receives on a chip, packetized data within the encoded video stream;

said at least one processor determines on said chip, an identifier within said received packetized data that defines one of a plurality of encoding types associated with packets in the encoded video stream;

said at least one processor selects on said chip, a decoding process from a plurality of decoding processes based on said determined identifier; and

said at least one processor decodes on said chip, at least a portion of said received packetized data in the encoded video stream utilizing said selected decoding process.

22. The system according to claim 21, wherein said at least one processor determines on said chip, a start code within said received packetized data that separates packets within the encoded video stream.

23. The system according to claim 22, wherein said at least one processor matches a plurality of bytes within said received packetized data with a determined byte sequence.

24. The system according to claim 23, wherein said at least one processor removes said plurality of bytes from said received packetized data, if said plurality of bytes matches said determined byte sequence.

25. The system according to claim 21, wherein said at least one processor decodes said at least a portion of said received packetized data utilizing at least one of a fixed length coding (FLC) process, a variable length coding (VLC) process and a context adaptive binary arithmetic coding (CABAC) process, if said determined identifier corresponds to H.264 video encoding.

26. The system according to claim 21, wherein said at least one processor decodes said at least a portion of said received packetized data utilizing at least one of a FLC process and a VLC process, if said determined identifier corresponds to VC-1 video encoding.

27. The system according to claim 21, wherein said at least one processor decodes said at least a portion of said received packetized data utilizing at least one of a FLC process and a VLC process, if said determined identifier corresponds to at least one of H.261, H.263, H.263+, MPEG-1, MPEG-2 and MPEG-4 video encoding.

28. The system according to claim 21, wherein said decoded packetized data comprises at least one of prediction pixels information and prediction error information.

29. The system according to claim 21, wherein said at least one processor generates a decoded video stream utilizing at least a portion of said decoded packetized data.

30. The system according to claim 29, wherein said at least one processor filters said generated decoded video stream utilizing at least one of an overlapped transform process and a deblocking process.

31. A method for processing an encoded video stream, the method comprising:

decoding header information from the encoded video stream utilizing a first CPU; and

decoding macroblock information from the encoded video stream utilizing a second CPU, while said first CPU decodes said header information.