Scan converter

• US 20050264691A1
• Filed: 03/31/2005
• Published: 12/01/2005
• Est. Priority Date: 05/31/2004
• Status: Active Grant

• Current Assignee: Panasonic Electric Works Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Asahi Matsushita Electric Works Ltd. (Panasonic Holdings Corporation)
• Inventors: Furukawa, Satoshi, Endo, Junpei, Hagio, Kenichi
• Granted Patent: US 7,349,027 B2
• Time in Patent Office: Days
• US Class Current: 348/446
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229

Abstract

The scan converter comprises first and second memories 3, 7, a frame. memory 5 having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit 8 for outputting the data from the memory 7 at a third transfer rate. The transfer rate between the memories 3, 7 and the memory 5 is twice as fast as the first or third transfer rate, whichever is faster, and the memories 3 has data storage capacities greater than an amount of the data to be written into the memory 5 in each write period, and the memories 7 has data storage capacities greater than an amount of the data to be read from the memory 5 in each read period.

Claims

1. A scan converter for converting progressive scan video data into interlaced scan video data comprising:

a first FIFO memory;

a second FIFO memory;

a frame memory having a write period and a read period;

a video data input means configured to take video data given from an image pickup means in a progressive scan mode and to write the video data at a first transfer rate into said first FIFO memory;

a write/read timing control means configured to set said frame memory alternately in the write period and the read period;

a data writing means configured to transfer the video data from said first FIFO memory to said frame memory at a second transfer rate within said write period;

a data reading means configured to transfer the video data from said frame memory to said second FIFO memory in an interlaced scan mode at the second transfer rate within the read period,

a video data output means configured to output the video data from said second FIFO memory at a third transfer rate;

wherein the second transfer rate is set to be at least twice as fast as the first transfer rate or the third transfer rate, whichever is faster,

said first FIFO memory having a data storage capacity greater than an amount of said video data to be written into said frame memory in each write period;

said second FIFO memory having a data storage capacity greater than an amount of said video data to be read out from said frame memory in each said read period.

2. The scan converter as set forth in claim 1, wherein the write/read timing control means switches between the write period and the read period in a period shorter than a period of a horizontal synchronizing signal of a standard television signal.

3. The scan converter as set forth in claim 1, further including

a memory address control means configured to control an address of said frame memory in which said data writing means writes the video data and from which said data reading means reads out the video data;

said frame memory having a data storage capacity of three or more frames, said frame memory being divided into two or more address areas each of which has a data storage capacity of one frame,

said memory address control means allocating one of the address areas to a write address area in which said data writing means writes the video data and switching the write address area in rotation,

said memory address control means allocating one of the address area which is different from the write address area to a read address area from which said data reading means reads out the video data.

4. The scan converter as set forth in claim 3, wherein

said memory address control means switches the write address area in synchronization with a vertical synchronizing signal of the video data sent from the image pickup means,

said memory address control means switching the read address area in synchronization with a vertical synchronizing signal of the standard television signal.

5. The scan converter as set forth in claim 3, wherein

said memory address control means allocates one of the address area which was allocated to the write address area immediately preceding the current write address area to the read address area.

6. The scan converter as set forth in claim 3, wherein

said memory address control means switches the read address area in synchronization with each field of the interlaced scan video data.

7. The scan converter as set forth in claim 1, wherein

said frame memory is DRAM, said frame memory being refreshed in a blanking period of the video data read out from the frame memory.

8. The scan converter as set forth in claim 1, wherein

the second transfer rate is set to be at least three times as fast as the first transfer rate or the third transfer rate, whichever is faster,

said data reading means being configured to read out a first video data which is not greater than one line and is to be outputted as the video data from the scan converter and a second video data which is not greater than one line and is adjacent to the first video data in a vertical direction,

said scan converter further including an arithmetic processing means which performs a computation using the first and the second video data.