Apparatus and method for providing a data interface to a plurality of radio transceivers

• US 20050266881A1
• Filed: 12/08/2004
• Published: 12/01/2005
• Est. Priority Date: 05/24/2004
• Status: Active Grant

• Current Assignee: United States Air Force
• Original Assignee: United States Air Force
• Inventors: Lutchansky, Nathan, Keppler, David
• Granted Patent: US 7,630,395 B2
• Time in Patent Office: Days
• US Class Current: 455/557
• CPC Class Codes: H04W 88/02 Terminal devices
• CPC Class Codes: H04W 92/18 between terminal devices

Abstract

Apparatus and method for providing a data interface to a plurality of radio transceivers such as between a personal computer or other information processing device to one or more radio transmitter/receiver systems having a serial data interface in a manner that provides control of the radio and means to send and receive data via the radio without regard to the characteristics of the radio or its serial interface. A common control protocol is employed that exposes the functionality necessary to control the radio transmitter/receiver device in a generic manner. The invention may communicate with the data terminal equipment via a widely-available data interface or network protocol, such as an asynchronous serial interface, the Universal Serial Bus (USB), or an Internet Protocol (IP) network. The invention also provides a means of implementing synchronous serial framing formats through software implementation, allowing compatibility with future data systems to be achieved without requiring hardware modifications.

Claims

1. Apparatus for interfacing data terminal equipment (DTE) to a plurality of radio transceiver types, comprising:

a central processing unit;

a data terminal interface; and

a radio serial interface;

wherein said central processing unit cooperates with said data terminal interface to exchange control and data signals with said data terminal equipment; and

wherein said central processing unit further cooperates with said radio serial interface to exchange data control signals with said plurality of radio transceiver types.

2. Radio serial interface of claim 1, further comprising:

a radio data serial interface; and

a radio control serial interface.

3. Radio data serial interface and radio control serial interface of claim 2, both further comprising:

a universal serial interface driver for converting the electrical signals of the serial interface port to the logic levels required by all said radio serial interface components;

a clock generator and a transmit clock selector switch for enabling synchronous operation by providing a transmit clock signal to a synchronous data sampler/driver;

a synchronous data sampler/driver which receives said selected transmit clock signal and when active, receives synchronous data from a data signal switch/multiplexer and passes said received data to said central processing unit and passes data to be transmitted from said central processing unit to a data signal switch/multiplexer;

a data signal switch/multiplexer which activates, receives data from and sends data to either said synchronous data sampler/driver or a universal asynchronous receiver/transmitter depending on whether a synchronous or asynchronous mode is selected, respectively; and

a universal asynchronous receiver/transmitter which, when active, receives asynchronous data from said data signal switch/multiplexer and passes said received data to said central processing unit and passes data to be transmitted from said central processing unit to said data signal switch/multiplexer.

4. Radio data serial interface of claim 3, further comprising a push-to-talk logic circuit for providing a selectable logic mapping between a push-to-talk signal generated by said central processing unit and the control signals on said radio data serial interface.

5. Transmit clock selector switch of claim 3 further providing a clock source from any of said serial interface transmit clock signal, said serial interface receive clock signal and said clock generator.

6. Synchronous data sampler/driver of claim 3, further comprising electronic reprogramming means to support a plurality of data formats.

7. Synchronous data sampler/driver of claim 6, further comprising;

a first general-purpose processing unit functioning as a sampler and a second general-purpose processing unit functioning as a driver;

said first general-purpose processing unit capable of reading data from said receive data signal at a clock cycle governed by said receive clock signal, wherein said data is converted and passed to said central processing unit for delivery to data terminal equipment;

said second general-purpose processing unit capable of receiving data from said central processing unit and delivering said data in serial on said transmit data signal at a clock cycle governed by said transmit clock signal; and

said first and said second general-purpose processing units being capable of determining serial data framing and synchronization so as to support a plurality of data formats.

8. Data terminal interface of claim 7, comprising a network interface for sending and receiving data between said central processing unit and data terminal equipment over a data network using a network protocol.

9. Data terminal interface of claim 7, comprising a universal serial bus interface for sending and receiving data between said central processing unit and data terminal equipment over a universal serial bus using a universal serial bus protocol.

10. Data terminal interface of claim 7, comprising a universal asynchronous receiver/transmitter for sending and receiving data between said central processing unit and data terminal equipment over an asynchronous serial bus using a serial link protocol.

11. Network protocol of claim 8 being a Transmission Control Protocol/Internet Protocol (TCP/IP).

12. Said apparatus for interfacing data terminal equipment (DTE) to a plurality of radio transceiver types of claim 11, further comprising

a common control protocol interpreter;

a first bidirectional TCP/IP port for carrying commands, responses and data to be transmitted by a radio transmitter between said DTE and said common control protocol interpreter;

a unidirectional TCP/IP port for carrying data received by a radio receiver;

a second bidirectional TCP/IP port for carrying radio control data between the DTE and the radio transmitter/receiver;

a first buffer between said common control protocol interpreter and the radio transmitter/receiver serial data port;

a second buffer between said unidirectional TCP/IP port and the radio transmitter/receiver serial data port; and

a third and a fourth buffer between said second bidirectional TCP/IP port and the radio transmitter/receiver serial control port.

13. Wherein said buffers of claim 12 accommodate DTE latency.

14. Said apparatus for interfacing data terminal equipment (DTE) to a plurality of radio transceiver types of claim 9, further comprising

a bidirectional USB serial port;

a common control protocol interpreter;

a first buffer;

a second buffer;

a bidirectional USB bus for carrying commands, responses and data to be transmitted by a radio transmitter between said DTE and said common control protocol interpreter and between said common control protocol interpreter and a said first buffer and between said first buffer and the radio transmitter/receiver; and

wherein said bidirectional USB bus further carries the data received by the radio transmitter/receiver to said second buffer and from said second buffer to said bidirectional USB serial port.

15. Wherein said buffers of claim 14 accommodate DTE latency.

16. Said apparatus for interfacing data terminal equipment (DTE) to a plurality of radio transceiver types of claim 10, further comprising

a bidirectional asynchronous USB serial port;

a first buffer;

a second buffer;

a bidirectional asynchronous USB bus for carrying control data between said DTE and said first buffer and between said first buffer and the radio transmitter/receiver; and

wherein said bidirectional USB bus further carries control data from the radio transmitter/receiver to said second buffer and from said second buffer to said bidirectional asynchronous USB serial port.

17. Wherein said buffers of claim 16 accommodate DTE latency.

23. A digital communications system, comprising:

a data terminal equipment (DTE);

a plurality of radio transmitter/receivers, each having a data interface and a control interface; and

a means according to claims 1 through 17 for interfacing said data terminal equipment (DTE) to said plurality of radio transmitter/receivers, wherein said means for interfacing is connected between each of said plurality of radio transmitter/receivers and said data terminal equipment (DTE).

24. Means for interfacing according to claim 23 being connected to data terminal equipment (DTE) via a data network.

25. Means for interfacing according to claim 23 being connected to data terminal equipment (DTE) via a USB link.

26. Means for interfacing according to claim 23 being connected to data terminal equipment (DTE) via an asynchronous serial link.

18. Method for interfacing data terminal equipment (DTE) to a plurality of radio transceiver types, comprising the steps of:

waiting in idle state for a command;

IF a command is received to activate the radio transmitter, THEN checking if data is currently being received;

IF data is not currently being received, THEN

sending a command acknowledgement to the DTE;

activating push-to-talk (PTT) signal;

waiting for a predetermined transmitter ramp-up period; and

returning to said step of waiting in idle state;

OTHERWISE,

waiting a predetermined amount of time for radio transmitter to be ready

OTHERWISE, continuing to wait in idle state for a command;

IF a command is received to send data via the radio transmitter, THEN

copying said data from the DTE and buffering said data in the radio transmitter; and

returning to said step of waiting in idle state;

OTHERWISE, continuing to wait in idle state for a command;

IF a command is received to deactivate the radio transmitter, THEN

flushing remaining data from the radio transmitter buffer;

checking for radio transmitter buffer to empty;

IF said radio transmitter buffer is not empty, THEN

returning to said step of flushing

OTHERWISE,

sending an acknowledgement to DTE that radio transmitter buffer is empty;

waiting a predetermined period of time for radio transmitter to become idle;

deactivating the push-to-talk (PTT) signal; and

returning to said step of waiting in idle state;

OTHERWISE, continuing to wait in idle state for a command; and

IF a command is received to query configuration parameters and statistics of the radio transmitter, THEN

querying and storing said configuration parameters and statistics;

sending an acknowledgement and value of said parameters and said statistics to the DTE; and

returning to said step of waiting in idle state;

OTHERWISE, continuing to wait in idle state for a command.

19. Method for synchronously driving data, comprising the steps of:

receiving a set of data bits to be transmitted from said DTE;

formatting said set of data bits into an internal buffer in accordance with an encoding scheme;

detecting a clock edge of a transmit clock signal;

transmitting the next bit of an internal buffer on a serial interface transmit signal upon detecting said clock edge of transmit clock signal; and

IF all bits of said internal buffer have been sent, THEN

returning to said step of receiving a set of data bits to be transmitted from said DTE;

OTHERWISE, returning to said step of detecting a clock edge of a transmit clock signal.

21. Wherein said set of data bits of claim 19 is an octet.

20. Method for synchronously sampling data, comprising the steps of:

detecting a clock edge of a receive clock signal;

sampling an incoming data bit from a serial receive signal;

IF the sampling process is synchronized with said receive signal data stream, THEN

decoding said incoming data bit according to a framing format; and

storing said decoded data bit in an internal buffer;

OTHERWISE, returning to said step of detecting a clock edge of a receive clock signal;

IF a complete set of data bits has been decoded, THEN

deliver said decoded set of data bits to the DTE; and

returning to said step of detecting a clock edge of a receive clock signal;

OTHERWISE,

returning to said step of detecting a clock edge of a receive clock signal.

22. Wherein said set of data bits of claim 20 is an octet.