Semiconductor device

• US 20050269642A1
• Filed: 12/20/2004
• Published: 12/08/2005
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Minami, Yoshihiro
• Granted Patent: US 7,154,151 B2
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device comprises a semiconductor substrate; an embedded insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the embedded insulating layer; a transistor including a first conductivity type source layer formed within the semiconductor layer, a first conductivity type drain layer formed in the semiconductor layer, and a channel forming region between the source layer and the drain layer; and an embedded insulating layer protective diode including a second conductivity type first diffusion layer and a first conductivity type second diffusion layer, the first diffusion layer being at the same potential as a semiconductor substrate region immediately below the channel forming region, the second diffusion layer being provided adjacently to the first diffusion layer and electrically connected to at least one of the source layer, the drain layer and the channel forming region.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

an embedded insulating layer provided on the semiconductor substrate;

a semiconductor layer provided on the embedded insulating layer;

a transistor including a first conductivity type source layer formed within the semiconductor layer, a first conductivity type drain layer formed in the semiconductor layer, and a channel forming region between the source layer and the drain layer; and

an embedded insulating layer protective diode including a second conductivity type first diffusion layer and a first conductivity type second diffusion layer, the first diffusion layer being at the same potential as a semiconductor substrate region immediately below the channel forming region, the second diffusion layer being provided adjacently to the first diffusion layer and electrically connected to at least one of the source layer, the drain layer and the channel forming region;

Wherein the semiconductor substrate is a second conductivity type, and the semiconductor substrate region immediately below toe channel forming region is a first conductivity type.

2. The semiconductor device according to claim 1, wherein

the first diffusion layer is provided within the semiconductor substrate,

wherein the second diffusion layer is provided within the first diffusion layer so as to be adjacent to the first diffusion layer.

3. The semiconductor device according to claim 1, wherein

the first diffusion layer is provided within the semiconductor layer,

wherein the second diffusion layer is provided within the semiconductor layer so as to be adjacent to the first diffusion layer.

4. The semiconductor device according to claim 1, wherein

the transistor further includes a gate electrode provided on a gate insulating film on the channel forming region,

the semiconductor device further comprising:

a gate insulating film protective diode including a second conductivity type third diffusion layer and a first conductivity type fourth diffusion layer, the third diffusion layer being at the same potential as the semiconductor substrate region immediately below the channel forming region and being provided within the semiconductor substrate, the fourth diffusion layer being provided within the third diffusion layer and electrically connected to the gate electrode.

5. The semiconductor device according to claim 2, wherein

the transistor further includes a gate electrode provided on a gate insulating film on the channel forming region,

the semiconductor device further comprising:

a gate insulating film protective diode including a second conductivity type third diffusion layer and a first conductivity type fourth diffusion layer, the third diffusion layer being at the same potential as a semiconductor substrate region immediately below the channel forming region and being provided within the semiconductor substrate, the fourth diffusion layer being provided within the third diffusion layer and electrically connected to the gate electrode.

6. The semiconductor device according to claim 3, wherein

the transistor further includes a gate electrode provided on a gate insulating film on the channel forming region,

the semiconductor device further comprising:

a gate insulating film protective diode including a second conductivity type third diffusion layer and a first conductivity type fourth diffusion layer, the third diffusion layer being at the same potential as a semiconductor substrate region immediately below the channel forming region and being provided within the semiconductor substrate, the fourth diffusion layer being provided within the third diffusion layer and electrically connected to the gate electrode.

7. The semiconductor device according to claim 1, wherein

the transistor further includes a gate electrode provided on a gate insulating film on the channel forming region,

the semiconductor device further comprising:

a gate insulating film protective diode including a second conductivity type third diffusion layer and a first conductivity type fourth diffusion layer, the third diffusion layer being at the same potential as at least one of the source layer, the drain layer and the channel forming region and being provided within the semiconductor layer, the fourth diffusion layer being provided within the third diffusion layer and electrically connected to the gate electrode.

8. The semiconductor device according to claim 2, wherein

the transistor further includes a gate electrode provided on a gate insulating film on the channel forming region,

the semiconductor device further comprising:

a gate insulating film protective diode including a second conductivity type third diffusion layer and a first conductivity type fourth diffusion layer, the third diffusion layer being at the same potential as at least one of the source layer, the drain layer and the channel forming region and being provided within the semiconductor layer, the fourth diffusion layer being provided within the third diffusion layer and electrically connected to the gate electrode.

9. The semiconductor device according to claim 3, wherein

the transistor further includes a gate electrode provided on a gate insulating film on the channel forming region,

the semiconductor device further comprising:

a gate insulating film protective diode including a second conductivity type third diffusion layer and a first conductivity type fourth diffusion layer, the third diffusion layer being at the same potential as at least one of the source layer, the drain layer and the channel forming region and being provided within the semiconductor layer, the fourth diffusion layer being provided within the third diffusion layer and electrically connected to the gate electrode.

10. The semiconductor device according to claim 1, wherein

the semiconductor substrate region immediately below the channel forming region is connected to the first diffusion layer by a metal plug.

11. The semiconductor device according to claim 4, wherein

the semiconductor substrate region immediately below the channel forming region is connected to the third diffusion layer by a metal plug.

12. The semiconductor device according to claim 1, wherein

the transistor functions as a peripheral circuit element, input/output circuit element of a memory cell or the memory cell itself, the memory cell storing a data by accumulating charges in the channel forming region.

13. The semiconductor device according to claim 1, wherein

an interconnection, which is formed in a first layer of a multilayer wiring structure, connects between the source layer, the drain layer or the channel forming region and the second diffusion layer.

14. The semiconductor device according to claim 4, wherein

an interconnection, which is formed in a first layer of a multilayer wiring structure, connects between the source layer, the drain layer or the channel forming region and the second diffusion layer.

15. The semiconductor device according to claim 4, wherein

an interconnection, which is formed in a first layer of a multilayer wiring structure, connects between the gate electrode and the fourth diffusion layer.

16. The semiconductor device according to claim 7, wherein

an interconnection, which is formed in a first layer of a multilayer wiring structure, connects between the gate electrode and the fourth diffusion layer.