Single-stage buck-boost inverter

• US 20050270000A1
• Filed: 03/31/2005
• Published: 12/08/2005
• Est. Priority Date: 03/31/2004
• Status: Active Grant

• Current Assignee: University of New Brunswick
• Original Assignee: University of New Brunswick
• Inventors: Liu, Zhuomin, Chang, Liuchen
• Granted Patent: US 7,333,349 B2
• Time in Patent Office: Days
• US Class Current: 323/222
• CPC Class Codes: H02M 7/48 using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02E 10/56 Power conversion systems, e.g. maximum power point trackers
• CPC Class Codes: Y02E 10/76 Power conversion electric or electronic aspects

Abstract

An improved Single-Stage Buck-Boost inverter (S²B² Inverter) is provided, using only three or four power semiconductor switches and two coupled inductors in a flyback arrangement. The inverter can handle a wide range of dc input voltages and produce a fixed ac output voltage. The inverter is well suited to distributed power generation systems such as photovoltaic and wind power and fuel cells, for standalone or grid connected applications. The inverter has a single charge loop, a positive discharge loop and a negative discharge loop.

Claims

1. A single-stage buck-boost inverter, comprising:

an input for receiving DC power;

an output operable to provide AC power;

a first inductor;

a first switching means to controllably connect said first inductor to said input;

a first discharge loop for conveying power to said output;

a second switching means to controllably connect said first inductor to said first discharge loop;

a second inductor magnetically coupled to said first inductor;

a second discharge loop for conveying power to said output;

a third switching means to controllably connect said second inductor to said second discharge loop.

2. An inverter as claimed in claim 1, wherein said first discharge loop is operable to convey power during a positive half cycle of output and said second discharge loop is operable to convey power during a negative half cycle of output.

3. An inverter as claimed in claim 2, further comprising a control means for controlling said first, second and third switching means so as to generate an AC power signal at said output.

4. An inverter as claimed in claim 3, wherein said first switching means comprises a first semiconductor switch and a second semiconductor switch.

5. An inverter as claimed in claim 4, wherein said second switching means comprises said first semiconductor switch and a third semiconductor switch and said third switching means comprises said second semiconductor switch and a fourth semiconductor switch.

6. An inverter as claimed in claim 5, wherein each said first and second discharge loop further comprises an isolation diode to isolate said output from said input.

7. An inverter as claimed in claim 3, wherein said first switching means comprises one semiconductor switch.