Stackable semiconductor chip layer comprising prefabricated trench interconnect vias

• US 20050277288A1
• Filed: 06/10/2005
• Published: 12/15/2005
• Est. Priority Date: 11/11/1997
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Aprolase Development Co LLC (Intellectual Ventures LLC)
• Inventors: Boyd, W. Eric, Ozguz, Volkan, Yamaguchi, James, Albert, Douglas, Pepe, Angel, Camien, Andrew
• Granted Patent: US 7,786,562 B2
• Time in Patent Office: Days
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Claims

1. A method for making a stackable semiconductor chip layer comprising:

providing a semiconductor substrate having first surface and a second surface,

defining electronic circuitry on said first surface in a series of semiconductor process steps,

defining a trench having an interior surface on said first surface wherein said trench is defined concurrently with said electronic circuitry during and as part of said semiconductor process steps,

disposing a dielectric material upon said interior surface,

depositing an electrically conductive material upon said dielectric material,

removing a predetermined portion of said second surface whereby said conductive material is exposed to form an electrically conductive via.

2. The method of claim 1 wherein said trench is defined by a dry reactive ion etch process.

3. The method of claim 1 wherein said cavity is substantially filled with an electrically conductive material.

4. The method of claim 1 wherein said electrically conductive material is comprised of a doped polysilicon material.

5. The method of claim 1 wherein said electrically conductive material is a metal.

6. An electronic module comprised of:

a plurality of semiconductor chip layers made according to the method of claim 1,

said plurality of semiconductor chip layers stacked and bonded to form a module,

wherein said electronic circuitry of at least on of said plurality of said semiconductor chip layers is in electrical communication with said electronic circuitry of at least one other of said plurality of said semiconductor chips in said module by means of at least one electrically conducive via.

7. The electronic module of claim 6 further comprising at least one thermal management layer disposed between at least two of said plurality of semiconductor chip layers.

8. The electronic module of claim 7 wherein said at least one thermal management layer is comprised of a thermally conductive adhesive film.

9. The electronic module of claim 7 wherein said at least one thermal management layer is comprised of a thermally conductive epoxy.

10. The electronic module of claim 7 further comprising at least on T-connect.

11. The module of claim 7 wherein at least two of said plurality of semiconductor chip layers are bonded together with a Z-conductive epoxy.

12. A method for making a stackable semiconductor chip layer comprising:

providing a semiconductor substrate having a thickness and having first surface and a second surface,

defining electronic circuitry on said first surface in a series of semiconductor process steps to define one or more integrated circuit die,

defining a trench having an interior surface on at least one of said integrated circuit die wherein said trench is defined concurrently with said electronic circuitry during and as part of said semiconductor process steps,

disposing a dielectric material upon said interior surface of said trench,

depositing an electrically conductive material upon said dielectric material and within said trench,

defining a plurality of grooves into said first surface, said grooves penetrating into said first surface at a predetermined distance less than said thickness whereby said one or more integrated circuit dies remain integral with said substrate,

mounting said substrate to a flat rigid plate to support said substrate, said first surface of said substrate being releasably mounted to said plate,

removing a predetermined portion of said second surface whereby said thickness is reduced to expose said plurality of said grooves and to expose said electrically conductive material within said trench, said dies remaining mounted to said plate,

releasing said one or more dies from said plate.