Unmolded package for a semiconductor device

• US 20050280161A1
• Filed: 08/11/2005
• Published: 12/22/2005
• Est. Priority Date: 02/01/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Rajeev Joshi
• Inventors: Joshi, Rajeev
• Granted Patent: US 7,393,718 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15321 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.

Claims

1-10. -10. (canceled)

11. A method comprising:

obtaining a substrate comprising a first side and a second side;

attaching a semiconductor die comprising a periphery to the first side of the substrate, the semiconductor die comprising a first surface comprising a drain, and a second surface opposite the first surface, wherein the second surface comprises source and gate regions; and

attaching conductive structures to the substrate outside of the periphery of the semiconductor die, wherein ends of the conductive structures are substantially coplanar with the first and second surfaces of the semiconductor die and wherein the conductive structures provide communication between source and gate regions at the second surface of the semiconductor die and a printed circuit board, when the semiconductor die is coupled to the printed circuit board.

12. The method of claim 11 further comprising:

attaching the substrate to the printed circuit board using the conductive structures, wherein there is no underfill material between the substrate and the printed circuit board.

13. The method of claim 11 wherein the conductive structures comprise solder.

14. The method claim 11 wherein the substrate is an insulated metal substrate.

15. The method of claim 11 further comprising attaching a second die on the second side of the substrate.

16. A semiconductor device comprising:

a substrate comprising a first side and a second side;

a semiconductor die comprising a periphery and being coupled to the first side of the substrate, the semiconductor die comprising a first surface comprising an output region, and a second surface opposite the first surface, wherein the second surface comprises an input region; and

conductive structures coupled to the substrate outside of the periphery of the semiconductor die, wherein ends of the conductive structures are substantially coplanar with the first and second surfaces of the semiconductor die and wherein the conductive structures provide communication between the input region at the second surface of the semiconductor die and a printed circuit board, and

wherein the first surface of the semiconductor die comprising the output region is proximate the circuit board and the second surface comprising the input region is distal to the circuit board.

17. The semiconductor device of claim 16 wherein there is no underfill material between the substrate and the printed circuit board.

18. The semiconductor device of claim 16 wherein the conductive structures comprise solder.

19. The semiconductor device of claim 16 wherein the substrate is an insulated metal substrate.

20. The semiconductor device of claim 16 wherein the semiconductor die is a first die and wherein the semiconductor device comprises a second die on the second side of the substrate.

21. A method comprising:

obtaining a substrate comprising a first side and a second side;

attaching a semiconductor die comprising a periphery to the first side of the substrate, the semiconductor die comprising a first surface comprising an output region, and a second surface opposite the first surface, wherein the second surface comprises an input region; and

attaching conductive structures to the substrate outside of the periphery of the semiconductor die, wherein ends of the conductive structures are substantially coplanar with the first and second surfaces of the semiconductor die and wherein the conductive structures provide communication between the input region at the second surface of the semiconductor die and a printed circuit board when the semiconductor die is coupled to the circuit board.

22. The semiconductor device of claim 21 further comprising attaching the substrate to the printed circuit board using the conductive structures, wherein there is no underfill material between the substrate and the printed circuit board.

23. The semiconductor device of claim 21 wherein the conductive structures comprise solder.

24. The semiconductor device of claim 21 wherein the substrate is an insulated metal substrate.

25. The semiconductor device of claim 21 wherein the semiconductor die is a first die and wherein the method further comprises attaching a second die on the second side of the substrate.