Rectifier circuit and radio communication device

• US 20050282505A1
• Filed: 06/16/2005
• Published: 12/22/2005
• Est. Priority Date: 06/17/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ootaka, Shoji, Umeda, Toshiyuki
• Granted Patent: US 7,424,265 B2
• Time in Patent Office: Days
• US Class Current: 455/100
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

A rectifier circuit includes a bias circuit that outputs a direct-current voltage; a first MOS transistor that has a gate and a source; and a second MOS transistor that has a gate, a source, and a drain connected to the source of the first MOS transistor. Only the direct-current voltage is applied between the gate and the source of the first MOS transistor, and only the direct-current voltage being applied between the gate and the source of the second MOS transistor. The rectifier circuit also includes a coupling capacitor that has a first end which is connected to the source of the first MOS transistor, and a second end to which an alternating-current signal is input.

Claims

1. A rectifier circuit comprising:

a bias circuit that outputs a direct-current voltage;

a first MOS transistor that has a gate and a source, only the direct-current voltage being applied between the gate and the source of the first MOS transistor;

a second MOS transistor that has a gate, a source, and a drain connected to the source of the first MOS transistor, only the direct-current voltage being applied between the gate and the source of the second MOS transistor; and

a coupling capacitor that has a first end which is connected to the source of the first MOS transistor, and a second end to which an alternating-current signal is input.

2. The rectifier circuit according to claim 1, wherein the first and second MOS transistors are formed to have a triple well structure on a semiconductor substrate.

3. The rectifier circuit according to claim 1, wherein the first MOS transistor has a backgate connected to the source of the first MOS transistor, and

the second MOS transistor has a backgate connected to the source of the second MOS transistor.

4. The rectifier circuit according to claim 1, further comprising a smoothing capacitor connected between the drain of the first MOS transistor and the source of the second MOS transistor.

5. The rectifier circuit according to claim 1, wherein the bias circuit includes

a first bias circuit that applies the direct-current voltage between the gate and the source of the first MOS transistor;

and

a second bias circuit that applies the direct-current voltage between the gate and the source of the second MOS transistor.

6. The rectifier circuit according to claim 5, further comprising a direct-current voltage generator circuit that generates a reference direct-current voltage, wherein

each of the first and second bias circuits outputs the direct-current voltage based on the reference direct-current voltage.

7. The rectifier circuit according to claim 6, wherein

the first and second MOS transistors, and the direct-current voltage generator circuit are integrated in an integrated circuit chip, and

the reference direct-current voltage is substantially equal to a threshold level of at least one of the first and second MOS transistors.

8. The rectifier circuit according to claim 7, wherein the direct-current voltage generator circuit includes

a third MOS transistor that has a drain and source which are connected to each other;

and

a constant-current source that is connected to the drain of the third MOS transistor.

9. The rectifier circuit according to claim 8, wherein the direct-current voltage generator circuit uses a voltage between the drain and a source of the third MOS transistor as the reference direct-current voltage, the voltage between the drain and the source being generated by a constant-current flowing between the drain and the source of the third MOS transistor.

10. The rectifier circuit according to claim 8, wherein the third MOS transistor is formed in a ratio of a gate width to a gate length of at least one of the first and second MOS transistors.

11. The rectifier circuit according to claim 8, wherein the direct-current voltage generator circuit includes

a constant-current source that supplies a constant current;

and

a switching unit that is connected between the constant-current source and the third MOS transistor, and

the direct-current voltage generator circuit intermittently outputs the reference direct-current voltage by the switching unit.

12. The rectifier circuit comprising a first rectifier circuit and a second rectifier circuit, each of which has the same structure as that of the rectifier circuit according to claim 1, wherein

the first and second rectifier circuits are connected to be stacked with each other.

13. The rectifier circuit according to claim 1, wherein the direct-current voltage is variable.

14. The rectifier circuit according to claim 1, wherein the bias circuit includes a capacitor holding the direct-current voltage.

15. The rectifier circuit according to claim 1, wherein the bias circuit includes

a first switching unit that is connected to a predetermined voltage source;

a first capacitor that holds a voltage supplied through the first switching unit;

a second switching unit that is connected to the first capacitor, operation of the second switching unit being complementary with operation of the first switching unit; and

a second capacitor that holds a voltage supplied through the second switching unit, as the direct-current voltage.

16. A rectifier circuit comprising:

a first floating-gate transistor that has a control gate and a source which are connected to each other, a drain, and a first floating gate which holds a predetermined potential;

a second floating-gate transistor that has a control gate and a source which are connected to each other, a drain which is connected to the source of the first floating-gate transistor, and a second floating gate which holds a predetermined potential; and

a coupling capacitor that has a first end which is connected to the source of the first floating-gate transistor, and a second end to which an alternating-current signal is input.

17. The rectifier circuit according to claim 16, wherein

a potential at the first floating gate is substantially equal to a threshold level of the first floating-gate transistor, and

a potential at the second floating gate is substantially equal to a threshold level of the second floating-gate transistor.

18. The rectifier circuit according to claim 16, further comprising:

a first direct-current voltage source that is connected to the drain of the first floating-gate transistor;

a second direct-current voltage source that is connected to the drain of the second floating-gate transistor;

a third direct-current voltage source that is connected to the source of the second floating-gate transistor; and

a control unit that performs charging or discharging on each of the first and second floating gates by controlling each output voltage of the first, second, and third direct-current voltage sources.

19. A radio communication device comprising:

a loop antenna;

a rectifier circuit that includes

a bias circuit that outputs a direct-current voltage;

a first MOS transistor that has a gate and a source, only the direct-current voltage being applied between the gate and the source of the first MOS transistor;

a second MOS transistor that has a gate, a source, and a drain connected to the source of the first MOS transistor, only the direct-current voltage being applied between the gate and the source of the second MOS transistor; and

a coupling capacitor that has a first end which is connected to the source of the first MOS transistor, and a second end to which an alternating-current induced in the loop antenna is input;

a memory that stores tag identification information; and

a signal processing circuit that transmits and receives the tag identification information through the loop antenna based on a direct current rectified by the rectifier circuit.

20. The radio communication device according to claim 19, further comprising a battery that is charged by the direct current rectified by the rectifier circuit, wherein

the rectifier circuit, the memory, and the signal processing circuit are connected to the battery.

21. The radio communication device according to claim 20, further comprising a sensor, wherein

the signal processing circuit transmits a signal detected by the sensor, through the loop antenna.

22. The radio communication device according to claim 20, further comprising an input/output device, wherein

the signal processing circuit activates the input/output device according to a signal received through the loop antenna.