STRUCTURES AND METHODS FOR MANUFACTURING P-TYPE MOSFET WITHGRADED EMBEDDED SILICON-GERMANIUM SOURCE-DRAIN AND/OR EXTENSION

• US 20050285192A1
• Filed: 06/29/2004
• Published: 12/29/2005
• Est. Priority Date: 06/29/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Zhu, Huilong
• Granted Patent: US 7,288,443 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

P-type MOSFETs (PMOSFETs) are formed by encapsulating the gate with an insulator and depositing a germanium containing layer outside the sidewalls, then diffusing the germanium into the silicon-on-insulator layer or bulk silicon by annealing or by oxidizing to form graded embedded silicon-germanium source-drain and/or Extension (geSiGe-SDE). For SOI devices, the geSiGe-SDE is allowed to reach the buried insulator to maximize the stress in the channel of SOI devices, which is beneficial for ultra-thin SOI devices. Graded germanium profiles provide a method to optimize stress in order to enhance device performance. The geSiGe-SDE creates a compressive stress in the horizontal direction (parallel to the gate dielectric surface) and tensile stress in the vertical direction (normal to the gate dielectric surface) in the channel of the PMOSFET, therebyforming a structure that enhances PMOSFET performance.

Claims

1. A method of forming a PMOSFET comprising the steps of:

providing an SOI wafer having a buried insulator layer and a SOI layer above said buried insulator layer;

forming a layer of gate insulator over said SOI layer;

forming a transistor gate over said SOI layer having a channel underneath said gate;

forming insulator sidewalls on first and second sides of said gate;

epitaxially forming a doped layer containing a dopant on said SOI layer and adjacent to said insulator sidewalls;

diffusing said dopant into said SOI layer from said doped layer, thereby producing compressive stress in the horizontal direction parallel to an SOI surface and tensile stress in a vertical direction normal to said SOI surface in said channel; and

completing said PMOSFET.

2. A method according to claim 1, in which said step of diffusing is effected by a high temperature anneal.

3. A method according to claim 1, in which said step of diffusing continues until said germanium reaches a bottom surface of said SOI layer.

4. A method according to claim 1, in which said step of diffusing stops before said germanium reaches a bottom surface of said SOI layer.

5. A method according to claim 1, in which said doped layer is SiGe.

6. A method according to claim 3, in which said dopant layer is SiGe with a Germanium concentration of greater than atomic number 20%.

7. A method according to claim 1, further comprising growing a layer of thermal oxide on said doped layer, thereby diffusing said dopant in the doped layer into said SOI layer.

8. A method according to claim 7, further comprising a step of removing said thermal oxide after said step of diffusing said dopant.

9. A method according to claim 7, in which said step of diffusing continues until said germanium reaches a bottom surface of said SOI layer.

10. A method according to claim 7, in which said step of diffusing stops before said dopant reaches a bottom surface of said SOI layer.

11. A method according to claim 7, in which said doped layer is SiGe.

12. A method according to claim 11, in which said doped layer is SiGe with a germanium concentration of greater than atomic number 20%.

13. A method of forming a PMOSFET comprising the steps of:

providing a bulk silicon wafer;

forming a layer of gate insulator over said bulk silicon;

forming a transistor gate over said bulk silicon having a channel underneath said gate;

forming insulator sidewalls on first and second sides of said gate;

epitaxially forming a doped layer containing germanium or impurity on said bulk silicon and adjacent to said insulator sidewalls;

diffusing germanium into said bulk silicon from said germanium doped layer, thereby producing compressive stress in horizontal direction (parallel to SOI surface) and tensile stress in vertical direction (in normal of SOI surface) in said channel; and

completing said PMOSFET.

14. A method according to claim 13, in which said step of diffusing is effected by a high temperature anneal.

15. A method according to claim 13, in which said doped layer is SiGe.

16. A method according to claim 13, in which said dopant layer is SiGe with a germanium concentration of greater than atomic number 20%.

17. A method according to claim 13, further comprising growing a layer of thermal oxide on said dopant layer, thereby diffusing said dopant into said bulk silicon.

18. A method according to claim 17, further comprising a step of removing said thermal oxide after said step of diffusing said dopant.

19. A method according to claim 17, in which said dopant layer is SiGe.

20. A method according to claim 19, in which said dopant layer is SiGe with a germanium concentration of greater than atomic number 20%.

21. An integrated circuit containing at least one PMOSFET formed in an SOI wafer having a buried insulator layer and a SOI layer above said buried insulator layer;

said at least one PMOSFET having a gate insulator over said SOI layer;

a transistor gate over said SOI layer having a channel underneath said gate, said channel having compressive stress in the horizontal direction parallel to an SOI surface and tensile stress in a vertical direction normal to said SOI surface in said channel; and

wherein said SOI layer has a graded concentration of a dopant that generates said compressive stress in said horizontal direction, said concentration of said dopant having a maximum value at an upper surface of said SOI layer.

22. An integrated circuit according to claim 21, in which said graded concentration of dopant extends to a dopant depth less than a thickness of said SOI layer.

23. An integrated circuit according to claim 22, in which said SOI layer is silicon and said dopant is Germanium.

24. An integrated circuit according to claim 22, in which said graded concentration is formed by a high temperature anneal.

25. An integrated circuit according to claim 22, in which said graded concentration is formed by thermally oxidizing a deposited dopant layer disposed above said SOI layer.