Ultra thin dual chip image sensor package structure and method for fabrication

• US 20050285239A1
• Filed: 06/29/2004
• Published: 12/29/2005
• Est. Priority Date: 06/29/2004
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Tsai, Chen Jung, Lin, Chih-Wen
• Granted Patent: US 7,045,888 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A thin stacked image sensor package containing an image sensor chip and a peripheral chip. A support pad for the peripheral chip adheres to a top surface of the peripheral chip, eliminating the need for a support member that otherwise would contribute to the thickness of the package. Thermal dissipation is enhanced by exposing surfaces including a back surface of the peripheral chip.

Claims

1. A dual chip stacked package, comprising:

a peripheral chip having a first active surface and a corresponding first back surface, the first active surface comprising a first plurality of bonding pads;

a leadframe comprising a plurality of leads having bonding surfaces and non-bonding surfaces and further comprising a supporting pad that includes at least one elongated chip supporting bar, the supporting pad being adhered to the first active surface in such a way as not to interfere with the first plurality of bonding pads;

an image sensor chip having a second active surface and a corresponding second back surface, the second active surface comprising a light receiving area and a peripheral area with a second plurality of bonding pads and the second back surface being secured to the supporting pad;

a plurality of wires, parts of which electrically connect with the first plurality of bonding pads and the leads, and parts of which electrically connect with the second plurality of bonding pads and the leads;

an encapsulation at least partially encompassing the leadframe, plurality of wires, peripheral chip, and image sensor chip, and forming a cavity over the second active surface to at least partially expose the light receiving area; and

a transparent lid disposed over the cavity to direct light to the light receiving area.

2. The dual chip stacked package as set forth in claim 1, wherein the supporting pad is attached to the first active surface by a liquid or solid non-conductive adhesive.

3. The dual chip stacked package as set forth in claim 1, wherein the second back surface is attached to the supporting pad by a liquid or solid adhesive.

4. The dual chip stacked package as set forth in claim 1, wherein the transparent lid comprises one or more of a flat shape, a convex shape and concave shape.

5. The dual chip stacked package as set forth in claim 1, wherein the first back surface is exposed to enhance thermal dispersion.

6. The dual chip stacked package as set forth in claim 1, wherein the non-bonding surfaces of the plurality of leads are exposed to enhance thermal dispersion and to facilitate connection to an external substrate.

7. The dual chip stacked package as set forth in claim 1, wherein the transparent lid is formed to have a cavity shape and the transparent lid is directly attached onto the encapsulation and leadframe.

8. A method of fabricating a package, comprising:

providing a peripheral chip having a first active surface including a first plurality of bonding pads disposed thereon, and having a corresponding first back surface;

providing a leadframe having a plurality of leads including bonding surfaces and non-bonding surfaces, and having a supporting pad that includes at least one elongated chip supporting bar;

attaching the supporting pad to the first active surface in such a way as not to interfere with the first plurality of bonding pads;

connecting wires between the first plurality of bonding pads and parts of the leads;

providing an image sensor chip having a second active surface and a corresponding second back surface, wherein the second active surface comprises a light receiving area and a peripheral area having a second plurality of bonding pads;

attaching the image sensor chip to the supporting pad;

connecting wires between the second plurality of bonding pads and parts of the leads;

forming a transparent lid over the light receiving area to direct light to the light receiving area.

9. The method as set forth in claim 8, wherein the attaching of the image sensor chip comprises attaching the image sensor chip to the at least one elongated chip supporting bar.

10. The method as set forth in claim 9, wherein:

the image sensor chip is attached to the at least one elongated chip supporting bar via the chip supporting pad; and

the at least one chip supporting bar comprises a plurality of chip supporting bars.

11. The method as set forth in claim 8, wherein the attaching of the image sensor chip comprises attaching the second back surface of the image sensor chip to the supporting pad by a liquid or solid adhesive.

12. The method as set forth in claim 8, wherein the forming of a transparent lid is preceded by at least partially encapsulating the leadframe, wires, peripheral chip, and image sensor chip, and forming a cavity over the second active surface to at least partially expose the light receiving area.

13. The method as set forth in claim 12, wherein the forming of a transparent lid comprises forming a transparent lid to have a cavity shape and attaching the transparent lid directly onto at least one of the encapsulation and the leadframe.

14. The method as set forth in claim 8, wherein the attaching of the supporting pad to the first active surface comprises attaching the supporting pad with a liquid or solid non-conductive adhesive.

15. The method as set forth in claim 8, wherein the first back surface is exposed to enhance thermal dispersion.

16. The dual method as set forth in claim 8, wherein the non-bonding surfaces of the plurality of leads are exposed to enhance thermal dispersion and to provide connection to an external printed circuit board.

17. The method as set forth in claim 8, wherein the forming of a transparent lid comprises forming a transparent lid to have a cavity shape and attaching the transparent lid directly onto the leadframe.

18. The method as set forth in claim 8, wherein a portion of the second back surface is exposed to enhance thermal dispersion.

19. An image sensor package produced by the method as set forth in claim 8.

20. An image sensor package produced by the method as set forth in claim 12.