Semiconductor device

• US 20050285659A1
• Filed: 08/12/2005
• Published: 12/29/2005
• Est. Priority Date: 08/31/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kanno, Yusuke, Yanagisawa, Kazumasa, Mizuno, Hiroyuki
• Granted Patent: US 7,375,574 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

Claims

1. A semiconductor device including a differential level converter circuit that receives a first signal and a phase-inverted signal of the first signal and outputs a second signal of a larger amplitude than an amplitude of the first signal, the differential level converter circuit comprises a first MISFET pair of first conductivity type for receiving the first signal and the phase-inverted signal of the first signal;

a second MISFET pair of first conductivity type for improving a withstand voltage of the first MISFET pair;

a third MISFET pair of second conductivity type having cross-coupled gates for latching the second signal to output; and

a forth MISFET pair of second conductivity type for ensuring the withstand voltage of the first MISFET pair,

wherein a film thickness of gate insulating films of the second MISFET pair is thicker than a film thickness of gate insulating films of the first MISFET pair;

wherein a film thickness of gate insulating films of the third MISFET pair is thicker than the film thickness of the gate insulating films of the first MISFET pair;

wherein an absolute value of a threshold voltage of the second MISFET pair is smaller than an absolute value of a threshold voltage of the third MISFET pair;

wherein an absolute value of a threshold voltage of the first MISFET pair is smaller than the absolute value of the threshold voltage of the third MISFET pair;

wherein a drain of one of the fourth MISFET pair is coupled to a drain of one of the first MISFET pair and the first signal is inputted to a gate of the one of the fourth MISFET pair; and

wherein a drain of another of the fourth MISFET pair is coupled to a drain of another of the first MISFET pair and the phase-inverted signal of the first signal is inputted to a gate of the another of the fourth MISFET pair.

2. The semiconductor device according to claim 1,

wherein the film thickness of gate insulating films of the second MISFET pair is thicker than a film thickness of gate insulating films of the fourth MISFET pair;

wherein a film thickness of gate insulating films of the third MISFET pair is thicker than the film thickness of the gate insulating films of the fourth MISFET pair;

wherein an absolute value of a threshold voltage of the fourth MISFET pair is smaller than the absolute value of the threshold voltage of the third MISFET pair.

3. The semiconductor device according to claim 2, wherein the gate insulating films of the second MISFET pair and the third MISFET pair are formed in one process and the insulating films of the first MISFET pair and the fourth MISFET pair are formed in another process.

4. The semiconductor device according to claim 1, wherein a source-drain path of one MISFET of the each of the first to third MISFET pairs is connected in series and a source-drain path of the other MISFET of each of the first to third MISFET pairs is also connected in series, such that the second MISFET pair is arranged between the first MISFET pair and the third MISFET pair.

5. The semiconductor device according to claim 1, wherein the gate insulating films of the first MISFET pair are made of a material with a dielectric constant higher than the dielectric constant of silicon dioxide.

6. The semiconductor device according to claim 1, wherein the differential level converter circuit outputs a first differential output from one drain of the third MISFET pair and a second differential output from the other drain of the third MISFET pair, and the semiconductor device further includes a level transition detector that detects and outputs a first in-time edge transition of one of the first differential output and the second differential output.

7. The semiconductor device according to claim 6, wherein the level transition detector includes an RS flip-flop, an inverter, an OR gate, and a NAND gate, the first differential output is input to a first input node of the RS flip-flop and the inverter, the second differential output is input to a second input node of the RS flip-flop and a first input node of the OR gate, an output of the RS flip-flop is input to a second input node of the OR gate, and an output of the OR gate and an output of the inverter are input to the NAND gate.

8. The semiconductor device according to claim 6, wherein the level transition detector includes an RS flip-flop, a NAND gate, and a D flip-flop, the first differential output is input to a first input node of the RS flip-flop, the second differential output is input to a second input node of the RS flip-flop, a phase-inverted signal of the first differential input is input to a first input node of the NAND gate, a phase-inverted signal of the second differential input is input to a second input node of the NAND gate, an output of the NAND gate is input to the D flip-flop as a clock;

and an output of the RS flip-flop is input to the D flip-flop as data.

9. The semiconductor device according to claim 1, wherein the first MISFET pair and the second MISFET pair are N-channel MISFETs, and the third MISFET pair and the fourth MISFET pairs are P-channel MISFETS.

10. A semiconductor device including a level converter circuit that receives a first signal with an amplitude of a first voltage and outputs a second signal with an amplitude of a second voltage which is larger than the first voltage, said first voltage being defined between a first potential and a second potential and said second voltage being defined between the first potential and a third potential;

wherein the level converter circuit comprises a first MISFET, a second MISFET and a third MISFET with source-drain paths therein connected in series having the second voltage applying therebetween;

a fourth MISFET, a fifth MISFET and a sixth MISFET with source-drain paths therein connected in series having the second voltage applying therebetween;

a seventh MISFET with source-drain path between a drain of the first MISFET and the second potential, and a eighth MISFET with source-drain path between a drain of the fourth MISFET and the second potential,

wherein the first, second, fourth and fifth MISFETs are first conductivity type and the third, sixth, seventh and eights MISFETs are second conductivity type,

wherein the first, second and seventh MISFETS receive the first signal at gates therein;

the fourth, fifth and eighth MISFETs receive a phase-inverted signal of the first signal at gates therein,

wherein a gate of the third MISFET is coupled to a drain of the sixth MISFET;

a gate of the sixth MISFET is coupled to a drain of the third MISFET,

wherein each of the second, third, fourth and fifth MISFETs has a gate insulating film thicker than the gate insulating film of each of the first, fourth, seventh and eights MISFETs; and

each of the second and fifth MISFETs has a threshold voltage lower than a threshold voltage of each of the first, third, fourth and sixth MISFETS.

11. The semiconductor device according to claim 10, wherein the gate insulating film of each of the first, fourth, seventh and eighth MISFETs is formed in one manufacturing process;

and the gate insulating film of each of the second, third, fourth and fifth MISFETS is formed in another manufacturing process.

12. The semiconductor device according to claim 10, wherein the differential level converter circuit outputs a first differential output from a drain of the third MISFET and a second differential output from a drain of the sixth MISFET, and the semiconductor device further includes a level transition detector that detects and outputs a first-in-time edge transition of one of the first differential output and the second differential output.

13. The semiconductor device according to claim 12 wherein the level transition detector includes an RS flip-flop, an inverter, an OR gate, and a NAND gate, the first differential output is input to a first input node of the RS flip-flop and the inverter, the second differential output is input to a second input node of the RS flip-flop and a first input node of the OR gate, an output of the RS flip-flop is input to a second input node of the OR gate, and an output of the OR gate and an output of the inverter are input to the NAND gate.

14. The semiconductor device according to claim 12, wherein the level transition detector includes an RS flip-flop, a NAND gate, and a D flip-flop, the first differential output is input to a first input node of the RS flip-flop, the second differential output is input to a second input node of the RS flip-flop, a phase-inverted signal of the first differential input is input to a first input node of the NAND gate, a phase-inverted signal of the second differential input is input to a second input node of the NAND gate, an output of the NAND gate is input to the D flip-flop as a clock;

and an output of the RS flip-flop is input to the D flip-flop as data.

15. The semiconductor device according to claim 10, wherein the first conductivity type is N type and the second conductivity type is P type.