Stacked transistor method and apparatus
First Claim
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1. An integrated RF Power Amplifier (PA) circuit, comprising:
- a) an input node to accept an input signal with respect to a reference voltage Vref, coupled to a gate G1 of a first FET M1;
b) a plurality of additional FETs M2 to Mn having a same polarity as M1 and coupled in series with M1 to form a control circuit configured to control conduction between the reference voltage and an output drive node, wherein FETs M2 to Mn are each enslaved to M1; and
c) an output coupling capacitor coupling the output drive node to an output load node.
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Abstract
A method and apparatus is described for controlling conduction between two nodes of an integrated circuit via a stack of FETs of common polarity, coupled in series. In an RF Power Amplifier (PA) having appropriate output filtering, or in a quad mixer, stacks of two or more FETs may be used to permit the use of increased voltages between the two nodes. Power control for such RF PAs may be effected by varying a bias voltage to one or more FETs of the stack. Stacks of three or more FETs may be employed to control conduction between any two nodes of an integrated circuit.
61 Citations
24 Claims
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1. An integrated RF Power Amplifier (PA) circuit, comprising:
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a) an input node to accept an input signal with respect to a reference voltage Vref, coupled to a gate G1 of a first FET M1;
b) a plurality of additional FETs M2 to Mn having a same polarity as M1 and coupled in series with M1 to form a control circuit configured to control conduction between the reference voltage and an output drive node, wherein FETs M2 to Mn are each enslaved to M1; and
c) an output coupling capacitor coupling the output drive node to an output load node. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit including a multiple-FET stack circuit for controlling conduction between a drive output node Vdrive and a reference voltage node Vref under control of an input signal applied between an input signal node and Vref, the integrated circuit comprising:
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a) a series stack of J same-polarity FETs MN, N an integer between 1 and J and J an integer 3 or greater, each FET MN having a source SN, a gate GN and a drain DN, b) an input signal node coupled to the gate G1 of a signal-input FET M1 of the FET stack;
c) for 0<
N<
J, a series coupling between each drain DN and the source S(N+1) of a next higher FET M(N+1) of the FET stack;
d) for 1<
N J, a gate coupling between each gate GN and at least one lower FET M(N−
K), K an integer between 1 and (N−
1), in a configuration enslaving each FET M(N+1) to M1 so as to conduct substantially concurrently with, and under control of, conduction in M1;
e) a source coupling for the FET stack between S1 and Vref; and
f) a drain coupling for the FET stack between DJ and Vdrive. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. An RF power amplifier (PA) circuit configured for operation at a center frequency F0, the PA circuit integrated onto a monolithic substrate and comprising:
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a) a stack of J FETs MN, for each integer value of N between 1 and J, J an integer greater than one, each FET MN having a source SN, a gate GN and a drain DN, the stack configured to control an output signal Vdrive with respect to a reference voltage Vref at a characteristic impedance of Zdrive, the FET stack including i) an input signal node coupled to the gate G1 of a lowest FET M1, ii) channel couplings from the source SN of each FET MN, for N>
1, to the drain D(N−
1) of a next lower FET M(N−
1),iii) gate couplings from DN of each FET MN;
for N>
1, to a lower FET so as to cause MN to conduct substantially concurrently with M1,iv) a FET stack reference coupling between S1 and Vref, and v) a FET stack output coupling between DJ and Vdrive; and
b) a shunt filter circuit configured to effect a shunt path between Vref and Vdrive having a local minimum impedance at approximately a harmonic frequency of F0. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification