METHOD OF MANUFACTURE OF SEMICONDUCTOR DEVICE

• US 20050287732A1
• Filed: 06/06/2005
• Published: 12/29/2005
• Est. Priority Date: 06/25/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Nakazawa, Yoshito, Kubo, Sakae
• Granted Patent: US 7,271,068 B2
• Time in Patent Office: Days
• US Class Current: 438/212
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film, by patterning the polycrystalline silicon film, in an active cell area, a gate electrode is formed within the groove portion, and the inside of the groove portion is embedded in a gate wiring area. Extending to the outside of the groove portion continuously out of the groove portion, there is a gate drawing electrode electrically connected to the gate electrode. Slits extending from the end portion of the gate drawing electrode are formed in the gate drawing electrode outside of the groove portion. Then, a silicon oxide film and a BPSG film are deposited on the substrate.

Claims

1. A manufacturing method of a semiconductor device, comprising the steps of:

(a) forming a first semiconductor layer of a first electric conduction type in a main surface of a semiconductor substrate of the first electric conduction type;

(b) forming a second semiconductor layer of a second electric conduction type by introducing impurities of the second electric conduction type of a polarity contrary to the first electric conduction type into the semiconductor substrate;

(c) in the main surface of the semiconductor substrate, forming a first groove portion that penetrates the second semiconductor layer in a first area, and forming a second groove portion that penetrates the second semiconductor layer in a second area;

(d) forming a first insulation film in the first groove portion and in the second groove portion;

(e) forming a first conductivity film over the semiconductor substrate under existence of the first insulation film, and embedding the first groove portion and the second groove portion by the first conductivity film;

(f) by patterning the first conductivity film, removing the first conductivity film being out of the first groove portion, and the first conductivity film only for the first depth from an opening of the first groove portion in the first area, and leaving the first conductivity film which embeds the second groove portion and extends and exists in determined amount out of the second groove in the second area,

(g) forming a third semiconductor layer of the first electric conduction type in the second semiconductor layer which adjoins the first groove portion by introducing impurities of the first electric conduction type into the second semiconductor layer of the first area;

(h) after the step (i), embedding the first groove portion, and forming a second insulation film over the semiconductor substrate so that a film thickness in the second area may become less than or equal to a film thickness in the first area;

(i) by patterning the second insulation film, removing the second insulation film being out of the first groove portion in the first area, and forming a first opening that reaches the first conductivity film extending and existing out of the second groove portion in the second insulation film in the second area; and

(j) after the step (i), forming a first wiring electrically connected to the third semiconductor layer over the semiconductor substrate of the first area, and forming a second wiring electrically connected to the first conductivity film under the first opening over the semiconductor substrate of the second area;

wherein in the first area, the first semiconductor layer is a drain, the second semiconductor layer is a channel, and the third semiconductor layer is a source.

2. A manufacturing method of a semiconductor device according to claim 1, wherein

the step (D) includes a step which forms a third groove portion in the first conductivity film extending and existing out of the second groove portion in the second area.

3. A manufacturing method of a semiconductor device according to claim 2, wherein

the third groove portion is formed so that it may become a same volume as a volume of the first groove portion over the first conductivity film.

4. A manufacturing method of a semiconductor device according to claim 3, wherein

a depth of the third groove portion is more than or equal to the first depth.

5. A manufacturing method of a semiconductor device according to claim 2, wherein

the first groove portion is formed so that two or more may be arranged in a first section of the semiconductor substrate in a first direction that intersects a direction which the first groove portion extends and exists;

the third groove portion is formed so that two or more may be arranged;

the width of the first groove portion and the width of the third groove portion are formed to become the same; and

in the first section, an interval of adjoining the first groove portions and an interval of adjoining the third groove portions are formed to become the same.

6. A manufacturing method of a semiconductor device according to claim 2, wherein

in plane form, the third groove portion is formed so that a direction which the first opening extends and exists may be intersected.

7. A manufacturing method of a semiconductor device according to claim 2, wherein

the third groove portion is formed so that plane form may be surrounded by the first conductivity film.

8. A manufacturing method of a semiconductor device according to claim 7, wherein

the third groove portion is formed so that plane form may become circular.

9. A manufacturing method of a semiconductor device according to claim 1, wherein

the first conductivity film is a gate.

10. A manufacturing method of a semiconductor device, comprising the steps of.

(a) forming a first semiconductor layer of a first electric conduction type in a main surface of a semiconductor substrate of the first electric conduction type;

(b) forming a second semiconductor layer of a second electric conduction type by introducing impurities of the second electric conduction type of a polarity contrary to the first electric conduction type into the semiconductor substrate;

(c) in the main surface of the semiconductor substrate, forming a first groove portion that penetrates the second semiconductor layer in a first area, and forming a second groove portion that penetrates the second semiconductor layer in a second area;

(d) forming a first insulation film in the first groove portion and in the second groove portion;

(e) forming a first conductivity film over the semiconductor substrate under existence of the first insulation film, and embedding the first groove portion and the second groove portion by the first conductivity film;

(f) by patterning the first conductivity film, removing the first conductivity film being out of the first groove portion, and the first conductivity film only for the first depth from an opening of the first groove portion in the first area, and leaving the first conductivity film which embeds the second groove portion and extends and exists in determined amount out of the second groove in the second area,

(g) forming a third semiconductor layer of the first electric conduction type in the second semiconductor layer which adjoins the first groove portion by introducing impurities of the first electric conduction type into the second semiconductor layer of the first area;

(h) after the step (f), forming a second insulation film which embeds the first groove portion over the semiconductor substrate;

(i) by patterning the second insulation film of the first area, removing the second insulation film being out of the first groove portion;

(j) before or after the step (i), by patterning the second insulation film of the second area, forming in the second insulation film a first opening that reaches the first conductivity film extending and existing out of the second groove portion; and

(k) after the step (i) and the step (j), forming a first wiring electrically connected to the third semiconductor layer over the semiconductor substrate of the first area, and forming a second wiring electrically connected to the first conductivity film under the first opening over the semiconductor substrate of the second area;

wherein in the first area, the first semiconductor layer is a drain, the second semiconductor layer is a channel, and the third semiconductor layer is a source.

11. A manufacturing method of a semiconductor device according to claim 10, wherein the first conductivity film is a gate.

12. A manufacturing method of a semiconductor device, comprising the steps of

(a) forming a first semiconductor layer of a first electric conduction type in a main surface of a semiconductor substrate of the first electric conduction type;

(b) forming a second semiconductor layer of a second electric conduction type by introducing impurities of the second electric conduction type of a polarity contrary to the first electric conduction type into the semiconductor substrate;

(c) in the main surface of the semiconductor substrate, forming a first groove portion that penetrates the second semiconductor layer in a first area, and forming a second groove portion that penetrates the second semiconductor layer in a second area;

(d) forming a first insulation film in the first groove portion and in the second groove portion;

(e) forming a first conductivity film over the semiconductor substrate under existence of the first insulation film, and embedding the first groove portion and the second groove portion by the first conductivity film;

(f) by patterning the first conductivity film, removing the first conductivity film being out of the first groove portion, and the first conductivity film only for the first depth from an opening of the first groove portion in the first area, and leaving the first conductivity film which embeds the second groove portion and extends and exists in determined amount out of the second groove in the second area,

(g) forming a third semiconductor layer of the first electric conduction type in the second semiconductor layer which adjoins the first groove portion by introducing impurities of the first electric conduction type into the second semiconductor layer of the first area;

(h) after the step (f), forming a second insulation film which embeds the first groove portion over the semiconductor substrate;

(i) etching the second insulation film over a whole surface of the semiconductor substrate until the second insulation film being out of the first groove portion is removed;

(j) repeating the step (h) and the step (i) until the first groove portion is embedded by the second insulation film after the step (i);

(k) after the step (h), forming a third insulation film over the semiconductor substrate;

(l) by patterning the third insulation film, removing the third insulation film in the first area, and forming in the third insulation film a first opening that reaches the first conductivity film extending and existing out of the second groove portion in the second area; and

(m) after the step (l), forming a first wiring electrically connected to the third semiconductor layer over the semiconductor substrate of the first area, and forming a second wiring electrically connected to the first conductivity film under the first opening over the semiconductor substrate of the second area;

wherein in the first area, the first semiconductor layer is a drain, the second semiconductor layer is a channel, and the third semiconductor layer is a source.

13. A manufacturing method of a semiconductor device according to claim 12, wherein

in a time of the step (l), a film thickness of the second insulation film of the second area is less than or equal to a film thickness of the second insulation film of the first area.

14. A manufacturing method of a semiconductor device according to claim 12, wherein

the first conductivity film is a gate.