Method for fabricating trench power device

• US 20050287734A1
• Filed: 10/08/2004
• Published: 12/29/2005
• Est. Priority Date: 06/25/2004
• Status: Active Grant

• Current Assignee: Mosel Vitelic Incorporated
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Chang, Jen-Chieh, Chung, Yi-Fu, Hung, Tun-Fu
• Granted Patent: US 7,118,971 B2
• Time in Patent Office: Days
• US Class Current: 438/232
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, a method for forming an oxide layer at the bottom of a trench comprises providing a first substrate with at least one trench therein; forming a first oxide layer on the bottom and sidewalls of the trench; removing the first oxide layer at the bottom of the trench; and forming a second oxide layer at the bottom of the trench.

Claims

1. A method for forming an oxide layer at the bottom of a trench, the method comprising:

providing a first substrate with at least one trench therein;

forming a first oxide layer on the bottom and sidewalls of the trench;

removing the first oxide layer at the bottom of the trench; and

forming a second oxide layer at the bottom of the trench.

2. The method as claimed in claim 1, wherein the first substrate is formed by:

providing a substrate;

forming a third oxide layer on the substrate;

forming a silicon nitride layer on the third oxide layer;

patterning the silicon nitride layer and the third oxide layer to form an opening; and

etching the substrate along the opening to form the trench therein.

3. The method as claimed in claim 1, wherein the first oxide is formed by thermal oxidation.

4. The method as claimed in claim 1, wherein the second oxide is formed by:

forming a fourth oxide layer on the first substrate filling the trench;

removing the fourth oxide layer on the first substrate and on the sidewalls of the trench; and

densification of the fourth oxide layer to form the second oxide layer.

5. The method as claimed in claim 4, wherein the fourth oxide layer is formed by chemical vapor deposition (CVD).

6. The method as claimed in claim 5, wherein the CVD is a high ozone-tetraethyloxysilane (O₃-TEOS) CVD process.

7. The method as claimed in claim 4, wherein removing the fourth oxide layer on the first substrate and on the sidewalls of the trench is performed by wet etching.

8. The method as claimed in claim 7, wherein the wet etching is performed by an HF based solution.

9. The method as claimed in claim 8, wherein the HF based solution is a buffered-oxide-etch (BOE) solution.

10. The method as claimed in claim 4, wherein the densification is performed by annealing.

11. The method as claimed in claim 1, wherein the first substrate comprises a silicon substrate.

12. The method as claimed in claim 1, wherein removing the first oxide layer at the bottom of the trench is performed by dry etching.

13. The method as claimed in claim 2, further comprising removing the remaining silicon nitride layer.

14. The method as claimed in claim 2, wherein the third oxide layer is formed by thermal oxidation.

15. The method as claimed in claim 2, wherein the silicon nitride layer is formed by chemical vapor deposition.

16. The method as claimed in claim 2, wherein patterning the silicon nitride layer comprises:

forming a photoresist layer on the silicon nitride layer;

exposing and developing the photoresist layer to expose the silicon nitride layer; and

removing the exposed the silicon nitride layer.

17. A method for fabricating a power device, the method comprising:

providing a substrate;

forming a third oxide layer on the substrate;

forming a silicon nitride layer on the third oxide layer;

patterning the silicon nitride layer and the third oxide layer to form an opening;

etching the substrate along the opening to form a trench therein;

forming a first oxide layer on the bottom and sidewalls of the trench;

removing the first oxide layer at the bottom of the trench; and

forming a second oxide layer at the bottom of the trench.

18. The method as claimed in claim 17, further comprising:

forming a dielectric layer in the trench; and

forming a conductive layer on the dielectric layer.

19. The method as claimed in claim 18, wherein the conductive layer comprises a polysilicon layer.

20. The method as claimed in claim 17, further comprising:

removing the third oxide layer;

forming a dielectric layer in the trench; and

forming a conductive layer on the dielectric layer.

21. The method as claimed in claim 20, wherein the conductive layer comprises a polysilicon layer.

22. The method as claimed in claim 17, wherein the first oxide layer is formed by thermal oxidation.

23. The method as claimed in claim 17, wherein the third oxide layer is formed by thermal oxidation.

24. The method as claimed in claim 17, wherein the second oxide is formed by:

forming a fourth oxide layer on the first substrate filling the trench;

removing the fourth oxide layer on the first substrate and on the sidewalls of the trench; and

densification of the fourth oxide layer to form the second oxide layer.

25. The method as claimed in claim 24, wherein the fourth oxide layer is formed by chemical vapor deposition (CVD).

26. The method as claimed in claim 25, wherein the CVD is a high ozone-tetraethyloxysilane (O₃-TEOS) CVD process.

27. The method as claimed in claim 24, wherein removing the fourth oxide layer on the first substrate and on the sidewalls of the trench is performed by wet etching.

28. The method as claimed in claim 27, wherein the wet etching is performed by an HF based solution.

29. The method as claimed in claim 28, wherein the HF based solution is a buffered-oxide-etch (BOE) solution.

30. The method as claimed in claim 24, wherein the densification is performed by annealing.

31. The method as claimed in claim 17, wherein the silicon nitride layer is formed by chemical vapor deposition.

32. The method as claimed in claim 17, wherein the substrate comprises a silicon substrate.

33. The method as claimed in claim 17, wherein removing the first oxide layer at the bottom of the trench is performed by dry etching.

34. The method as claimed in claim 17, wherein the power device is a trench power device.

35. The method as claimed in claim 17, wherein patterning the silicon nitride layer comprises:

forming a photoresist layer on the silicon nitride layer;

exposing and developing the photoresist layer to expose the silicon nitride layer; and

removing the exposed the silicon nitride layer.

36. A method for fabricating a power device, the method comprising:

providing a substrate;

forming a third oxide layer on the substrate;

forming a silicon nitride layer on the third oxide layer;

patterning the silicon nitride layer and the third oxide layer to form an opening;

etching the substrate along the opening to form a trench therein;

forming a first oxide layer on the bottom and sidewalls of the trench;

removing the first oxide layer at the bottom of the trench;

forming a second oxide layer at the bottom of the trench;

removing the remaining silicon nitride layer; and

removing the first oxide on the sidewalls of the trench and the remaining third oxide layer.

37. The method as claimed in claim 36, further comprising:

forming a dielectric layer in the trench; and

forming a conductive layer on the dielectric layer.

38. The method as claimed in claim 37, wherein the conductive layer comprises a polysilicon layer.

39. The method as claimed in claim 36, wherein the first oxide layer is formed by thermal oxidation.

40. The method as claimed in claim 36, wherein the third oxide layer is formed by thermal oxidation.

41. The method as claimed in claim 36, wherein the second oxide layer is formed by:

forming a fourth oxide layer on the first substrate filling the trench;

removing the fourth oxide layer on the first substrate and on the sidewalls of the trench; and

densification the fourth oxide layer to form the second oxide layer.

42. The method as claimed in claim 41, wherein the fourth oxide layer is formed by chemical vapor deposition (CVD).

43. The method as claimed in claim 42, wherein the CVD is a high ozone-tetraethyloxysilane (O₃-TEOS) CVD process.

44. The method as claimed in claim 41, wherein removing the fourth oxide layer on the first substrate and on the sidewalls of the trench is performed by wet etching.

45. The method as claimed in claim 44, wherein the wet etching is performed by an HF based solution.

46. The method as claimed in claim 45, wherein the HF based solution is a buffered-oxide-etch (BOE) solution.

47. The method as claimed in claim 41, wherein the densification is performed by annealing.

48. The method as claimed in claim 36, wherein the silicon nitride is formed by chemical vapor deposition.

49. The method as claimed in claim 36, wherein the substrate comprises a silicon substrate.

50. The method as claimed in claim 36, wherein removing the first oxide layer at the bottom of the trench and the remaining third oxide is performed by wet etching.

51. The method as claimed in claim 36, wherein the power device is a trench power device.

52. The method as claimed in claim 36, wherein patterning the silicon nitride layer comprises:

forming a photoresist layer on the silicon nitride layer;

exposing and developing the photoresist layer to expose the silicon nitride layer; and

removing the exposed the silicon nitride layer.