Lateral semiconductor device using trench structure and method of manufacturing the same

• US 20060001085A1
• Filed: 06/17/2005
• Published: 01/05/2006
• Est. Priority Date: 07/01/2004
• Status: Active Grant

• Current Assignee: Ablic Inc. (MinebeaMitsumi Inc.)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Risaki, Tomomitsu
• Granted Patent: US 7,242,058 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A lateral trench MOS transistor is provided in which trenches extending to the source and drain regions are disposed parallel to the gate length direction, agate oxide is disposed on the trenches, a well is disposed under the trench region and the source and drain regions by using oblique ion implantation, a gate electrode is disposed on the gate oxide, and source and drain regions are disposed on the same plane as a bottom surface of a concave portion of the trenches self-aligned to the gate electrode by using oblique ion implantation.

Claims

1. A semiconductor device, comprising:

a first trench region in which trenches whose lengthwise direction is parallel to a gate length direction are formed on a surface of a semiconductor substrate;

a second trench region and a third trench region which are provided on the same plane as a bottom surface of a concave portion of the first trench region to contact with both ends of the first trench region in its lengthwise direction;

a second conductivity type well region formed in the first trench region, the second trench region, and the third trench region;

a gate insulating film provided in the first trench region;

a gate electrode provided on the gate insulating film;

a first conductivity type source region which is provided shallower than the well region in a first portion of the first trench region and the second trench region; and

a first conductivity type drain region which is provided shallower than the well region in a second portion of the first trench region and the third trench region.

2. A semiconductor device according to claim 1, wherein the semiconductor device has a DDD structure.

3. A semiconductor device according to claim 1, wherein the semiconductor has an LDMOS structure.

4. A semiconductor device according to claim 1, wherein a width of a convex portion in the first trench region is approximately 1,000 Å

.

5. A semiconductor device according to claim 2, wherein a width of a convex portion in the first trench region is approximately 1,000 Å

.

6. A semiconductor device according to claim 3, wherein a width of a convex portion in the first trench region is approximately 1,000 Å

.

7. A semiconductor device according to claims 1, wherein the semiconductor device is formed by merging a twin well technology.

8. A semiconductor device according to claims 2, wherein the semiconductor device is formed by merging a twin well technology.

9. A semiconductor device according to claims 3, wherein the semiconductor device is formed by merging a twin well technology.

10. A semiconductor device according to claims 4, wherein the semiconductor device is formed by merging a twin well technology.

11. A semiconductor device according to claims 5, wherein the semiconductor device is formed by merging a twin well technology.

12. A semiconductor device according to claims 6, wherein the semiconductor device is formed by merging a twin well technology.

13. A method of manufacturing the semiconductor device according to claims 1, comprising the steps of:

forming the trench regions; and

forming the well region by oblique ion implantation in multiple directions.

14. A method of manufacturing the semiconductor device according to claims 1, comprising the steps of:

forming the trench regions; and

forming the source region and the drain region by oblique ion implantation in multiple directions.

15. A method of manufacturing the semiconductor device according,to claim 1, comprising the steps of:

forming a second conductivity type semiconductor region through ion implantation on the surface of the semiconductor substrate;

forming a semiconductor on the surface of the semiconductor substrate through epitaxial growth; and

forming a second conductivity type semiconductor region through ion implantation on a surface of the semiconductor formed through epitaxial growth.