Solid-state image pickup device, and manufacturing method thereof

• US 20060007336A1
• Filed: 09/12/2002
• Published: 01/12/2006
• Est. Priority Date: 09/12/2002
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamaguchi, Takumi
• Granted Patent: US 7,352,020 B2
• Time in Patent Office: Days
• US Class Current: 348/302
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H04N 25/626 Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers

Abstract

The present invention aims to provide a solid-state imaging apparatus that realizes less leakage current, high image quality and low noise during the driving operation, and manufacturing method for the same.

A MOS type imaging apparatus 1 includes an imaging region 10 and a driving region 20 both formed on a p-type silicon substrate (hereinafter called an “Si substrate”) 31.

The imaging region 10 includes six pixels 11 to 16 disposed in a shape of a matrix having 2 rows and 3 columns. The driving region 20 includes a timing generation circuit 21, a vertical shift resistor 22, a horizontal shift resistor 23, a pixel selection circuit 24, and so on.

All transistors included in the pixels 11 to 16 in the imaging region and the circuits 21 to 24 in the driving circuit region 20 are of n-channel MOS type.

Claims

1. A solid-state imaging apparatus that includes an imaging region and a drive circuit region both formed on one semiconductor substrate, the imaging region including an active-type unit pixel in which a photodiode unit generates signal charge by photoelectric conversion and an amplification unit amplifies the signal charge, the drive circuit region being for driving the photodiode unit and the amplification unit, the imaging region and the drive circuit region including one or more transistors respectively, wherein

the transistors in the imaging region and the drive circuit region have a same channel polarity.

2. The solid-state imaging apparatus according to claim 1, wherein

the transistors are of an n-channel MOS type.

3. The solid-state imaging apparatus according to claim 1, wherein

the drive circuit region includes a dynamic circuit that includes a capacitor for accumulating electric charge and a transistor for performing a switching function.

4. The solid-state imaging apparatus according to claim 3, wherein

the imaging region includes a plurality of active-type unit pixels, and

the drive circuit region includes a pixel selection circuit for selecting one active-type unit pixel from the plurality of active-type unit pixels and a shift resistor circuit for outputting a selection instruction signal to the pixel selection circuit.

5. The solid-state imaging apparatus according to claim 1, wherein

the imaging region includes a transistor for performing a switching function based on a signal received from the drive circuit region, and

the signal charge is output to the amplification unit while the transistor for performing the switching function is ON.

6. The solid-state imaging apparatus according to claim 1, wherein

the transistor is of a MOS type, of which a gate length is equal to or less than 0.6 μ

m.

7. The solid-state imaging apparatus according to claim 1, wherein

the transistor is of a MOS type, of which a film thickness of a gate insulator is in a range from 1 nm to 20 nm.

8. The solid-state imaging apparatus according to claim 1, wherein

the transistor is of a MOS type, and

an insulator that has a film thickness in a range from 1 nm to 20 nm and functions as a capacitor is formed between a gate electrode of the transistor and the semiconductor substrate.

9. A camera that includes the solid-state imaging apparatus according to claim 1.

10. A manufacturing method for a solid-state imaging apparatus, comprising steps of:

forming, on a semiconductor substrate, an imaging region including a photodiode unit for converting input light into signal charge and an amplification unit for amplifying the signal charge; and

forming, on the semiconductor substrate, a drive circuit region for driving the imaging region, wherein

MOS type transistors having a same channel polarity are formed in both steps for forming the imaging region and the drive circuit region respectively.

11. The manufacturing method for a solid-state imaging apparatus according to claim 10, wherein

the MOS type transistors formed in the both steps are of n-channel MOS type.

12. The manufacturing method for a solid-state imaging apparatus according to claim 10, wherein

a gate length of each MOS type transistor is equal to or less than 0.6 μ

m.

13. The manufacturing method for a solid-state imaging apparatus according to claim 10, wherein

a film thickness of a gate insulator in each MOS type transistor is in a range from 1 nm to 20 nm.

14. The manufacturing method for a solid-state imaging apparatus according to claim 10, wherein

an insulator that has a film thickness in a range from 1 nm to 20 nm and functions as a capacitor is formed between a gate electrode of each MOS type transistor and the semiconductor substrate.