Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same

• US 20060012042A1
• Filed: 09/20/2005
• Published: 01/19/2006
• Est. Priority Date: 06/27/2003
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hackitt, Dale, Taggert, Brian, Misra, Dilip K.
• Application Number:
  US11/230,858
• Publication Number:
  US 20060012042A1
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: C23C 30/00 Coating with metallic material characterised only by the composition of the metallic material, i.e. not characterised by the coating process C23C26/00, C23C28/00 take precedence
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45169 Platinum (Pt) as principal constituent
• CPC Class Codes: H01L 2224/45644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49866 characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 2203/049 : Wire bonding
• CPC Class Codes: H05K 2203/1572 : Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: H05K 3/244 : Finish plating of conductors, especially of copper conductors, e.g. for pads or lands selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3457, e.g. by plating H05K3/3473
• CPC Class Codes: H05K 3/3457 : Solder materials or compositions; Methods of application thereof
• CPC Class Codes: Y10T 428/24917 : including metal layer

Abstract

A wire-bonding substrate is described. The wire-bonding substrate includes a copper metallization and a gold surface finish disposed above and on the copper metallization. The gold surface finish completes a structure that includes at least one of a bond finger for wire bonding of a first side of the substrate, and a land pad for a ball attach on a second side of the substrate. A process of forming the surface finish is also disclosed. An electronic package is also disclosed that uses the surface finish on the wire-bonding substrate. A method of assembling an electronic package is also disclosed that includes the surface finish on the wire-bonding substrate. A computing system is also described that includes the surface finish on the wire-bonding substrate.

Claims

1-8. -8. (canceled)

9. A package comprising:

a wire bonding substrate including a first surface and a second surface, wherein the substrate includes at least one of;

a bond finger disposed on the first surface, wherein the bond finger includes a copper substrate, and a gold surface finish above and on the copper substrate; and

a land pad for a ball attach on the second surface, wherein the land pad includes a copper substrate, and a gold surface finish below and on the copper substrate; and

an electronic device, wherein the electronic device is wire-bonded to the bond finger.

10. The package according to claim 9, wherein the gold surface finish includes a first plating layer above and on the metallization, and a second plating layer above and on the first plating layer, and wherein the gold surface finish is in a thickness range from about 0.01 μ

m to about 10 μ

m.

11. The package according to claim 9, wherein the package is disposed in one of a computer, a wireless communicator, a hand-held device, an automobile, a locomotive, an aircraft, a watercraft, and a spacecraft.

12. A process comprising:

electroless plating a metallic surface finish upon a metallization, wherein the metallization is a layout that is disposed upon a wire-bonding substrate including a first surface and a second surface, and wherein the metallic surface finish includes at least one of;

a bond finger disposed on the first surface; and

a land pad for a ball attach on the second surface.

13. The process according to claim 12, wherein electroless plating a metallic surface finish upon a metallization includes:

plating a first layer above and on the metallization, wherein the first layer is selected from gold, silver, platinum, iridium, and combinations thereof.

14. The process according to claim 12, wherein electroless plating a metallic surface finish upon a metallization includes:

plating a first layer above and on the metallization; and

plating a second layer above and on the first layer, wherein the second layer has an equal or greater electrochemical potential than the first layer, and wherein the second layer is selected from gold, silver, platinum, iridium, and combinations thereof.

15. The process according to claim 12, wherein electroless plating a metallic surface finish upon a metallization includes:

plating a first layer above and on the metallization, wherein the first layer is in a thickness range from about 10 Å

to about 10,000 Å

; and

plating a second layer above and on the first layer, and wherein the metallic surface finish has an overall thickness in a range from about 0.01 μ

m to about 10 μ

m.

16. The process according to claim 12, wherein the metallization includes a copper metallization, wherein electroless plating a metallic surface finish upon a metallization includes:

plating a first layer above and on the metallization, wherein the first layer is selected from gold, gold alloy, silver, silver alloy, platinum, platinum alloy, iridium, iridium alloy, and combinations thereof, and wherein the first layer is in a thickness range from about 10 Å

to about 10,000 Å

; and

plating a second layer above and on the first layer, wherein the second layer has an equal or greater electrochemical potential than the first layer, and wherein the metallic surface finish has an overall thickness in a range from about 0.01 μ

m to about 10 μ

m.

17. A method comprising:

in a board layout array of wire-bonding substrates, in situ electrically testing a layout of an individual wire-bonding substrate.

18. The method according to claim 17, wherein testing includes simultaneously electrically testing more than one wire-bonding substrate.

19. The method according to claim 17, following testing, the method including:

rejecting and/or passing each board layout in the array; and

singulating each board layout from the array.

20. The method according to claim 17, following testing, the method including:

rejecting and/or passing each board layout in the array; and

wirebonding an electronic device to at least one board layout in the array.

21. The method according to claim 17, following testing, the method including:

rejecting and/or passing each board layout in the array;

wirebonding an electronic device to at least one board layout in the array;

followed by singulating each board layout from the array.

22. The method according to claim 17, following testing, the method including:

rejecting and/or passing each board layout in the array;

singulating each board layout from the array;

followed by

wirebonding an electronic device to at least one board layout from the board layout array.

23. The method according to claim 17, following testing, the method including:

rejecting and/or passing each board layout in the array;

wirebonding an electronic device to at least one board layout in the array to form a package; and

installing the package in a computing system, wherein the computing system is selected from a computer, a wireless communicator, a hand-held device, an automobile, a locomotive, an aircraft, a watercraft, and a spacecraft.

24. The method according to claim 17, following testing, the method including:

wirebonding an electronic device to at least one board layout in the array; and

singulating each board layout from the array.

25. A computing system comprising:

a wire bonding substrate including a first surface and a second surface, wherein the wire bonding substrate includes at least one of;

a bond finger disposed on the first surface, wherein the bond finger includes a copper substrate, and a gold surface finish above and on the copper substrate;

a land pad for a ball attach on the second surface, wherein the land pad includes a copper substrate, and a gold surface finish below and on the copper substrate;

an electronic device, wherein the electronic device is wire-bonded to the bond finger or the land pad for a ball attach; and

dynamic random-access data storage coupled to the electronic device.

26. The computing system according to claim 25, wherein the computing system is disposed in one of a computer, a wireless communicator, a hand-held device, an automobile, a locomotive, an aircraft, a watercraft, and a spacecraft.

27. The computing system according to claim 25, wherein the electronic device is selected from a data storage device, a digital signal processor, a micro controller, an application specific integrated circuit, and a microprocessor.