Semiconductor device

• US 20060017070A1
• Filed: 06/09/2005
• Published: 01/26/2006
• Est. Priority Date: 07/22/2004
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ikoma, Daisaku, Yamashita, Kyoji, Kajiya, Atsuhiro, Ootani, Katsuhiro
• Granted Patent: US 7,279,727 B2
• Time in Patent Office: Days
• US Class Current: 257/213
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor;

an element isolation region surrounding the diffusion region;

at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in a gate length direction;

an interlayer insulating film covering the gate electrode; and

a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has a dimension in the gate length direction larger than the gate interconnect part.

2. The semiconductor device according to claim 1, wherein

a plurality of said gate conductor films are provided on the diffusion region,

a plurality of said gate contacts are provided to connect to gate interconnect parts of the plurality of gate conductor films, respectively, and

the semiconductor device further comprises an interconnect which is formed on the interlayer insulating film and is in contact with the plurality of gate contacts.

3. The semiconductor device according to claim 2, further comprising conductor pads which are provided on the gate interconnect parts, respectively, each having a plane area larger than the gate contact,

wherein the gate contacts are in contact with the conductor pads, respectively.

4. The semiconductor device according to claim 3, wherein

each of the gate conductor films has an N-type polysilicon film containing an n-type impurity and a P-type polysilicon film containing a p-type impurity, and

each of the conductor pads is provided on the boundary between the N-type polysilicon film and the P-type polysilicon film and is overlapped with the N-type polysilicon film and the P-type polysilicon film.

5. The semiconductor device according to claim 1, wherein

a plurality of said gate conductor films are provided on the diffusion region, and

the gate contact is a common gate contact extending across gate interconnect parts of the plurality of gate conductor films.

6. The semiconductor device according to claim 5, wherein

each of the gate conductor films has an N-type polysilicon film containing an n-type impurity and a P-type polysilicon film containing a p-type impurity, and

the common gate contact is provided on the boundary between the N-type polysilicon film and the P-type polysilicon film and is overlapped with the N-type polysilicon film and the P-type polysilicon film.

7. The semiconductor device according to claim 2, wherein

each of the gate conductor films has an N-type polysilicon film containing an n-type impurity and a P-type polysilicon film containing a p-type impurity,

each of the gate contacts comprises a pair of gate contacts which are connected to gate interconnect parts of the N-type polysilicon film and the P-type polysilicon film, respectively, and

the interconnect is connected to all the gate contacts.

8. The semiconductor device according to claim 1, wherein

the gate conductor film has an N-type polysilicon film containing an n-type impurity and a P-type polysilicon film containing a p-type impurity,

the gate contact comprises a pair of gate contacts which are connected to gate interconnect parts of the N-type polysilicon film and the P-type polysilicon film, respectively, and

the interconnect is connected to the pair of gate contacts.

9. The semiconductor device according to claim 8, further comprising conductor pads which are provided on the gate interconnect parts, each having a plane area larger than the gate contact,

wherein the pair of gate contacts are in contact with the conductor pads, respectively.

10. The semiconductor device according to claim 1, further comprising a conductor pad which is provided on the gate interconnect part and has a plane area larger than the gate contact,

wherein the gate contact is in contact with the conductor pad.

11. The semiconductor device according to claim 10, further comprising source/drain contacts which pass through the interlayer insulating film and are connected to the diffusion region.