SINGLE POLY NON-VOLATILE MEMORY

• US 20060018161A1
• Filed: 01/19/2005
• Published: 01/26/2006
• Est. Priority Date: 07/20/2004
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Chen, Hsin-Ming, Wang, Shih-Chen, Tsai, Hong-Ping
• Granted Patent: US 7,209,392 B2
• Time in Patent Office: Days
• US Class Current: 365/185.280
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An erasable programmable non-volatile memory cell encompasses an ion well; a first select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a first floating gate channel region formed between its drain and source, and a common floating gate overlying the floating gate channel region; a second select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; and a second floating gate transistor having a drain, a source coupled to the drain of the second select transistor, a second floating gate channel region formed between its drain and source, and the common floating gate overlying the second floating gate channel region.

Claims

1. An erasable programmable non-volatile memory cell, comprising:

a first select transistor including a select gate, source/drain, and a first channel region formed between its source and drain, wherein a source line is electrically connected to its source;

a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a second channel region formed between its drain and source, and a floating gate overlying the second channel region;

a second select transistor including the said select gate, source/drain, and a third channel region formed between its source and drain, wherein the source of the second select transistor is coupled to the source line; and

a second floating gate transistor having a drain, a source coupled to the drain of the second select transistor, a fourth channel region formed between its drain and source, and the said floating gate overlying the fourth channel region.

2. The erasable programmable non-volatile memory cell according to claim 1 wherein the erasable programmable non-volatile memory cell is formed in an ion well.

3. The erasable programmable non-volatile memory cell according to claim 2 wherein the ion well is N type, the second floating gate transistor is a PMOS transistor.

4. The erasable programmable non-volatile memory cell according to claim 1 wherein the first select transistor, the second select transistor, and the first floating gate transistor are PMOS transistors.

5. The erasable programmable non-volatile memory cell according to claim 1 wherein the second select transistor and the second floating gate transistor are PMOS transistors, while the first select transistor and the first floating gate transistor are NMOS transistors.

6. The erasable programmable non-volatile memory cell according to claim 1 wherein the second floating gate transistor is a PMOS transistor, while the first select transistor, the second select transistor and the first floating gate transistor are NMOS transistors.

7. The erasable programmable non-volatile memory cell according to claim 1 wherein the first floating gate transistor, the second floating gate transistor, and the first select transistor are PMOS transistors, while the second select transistor is an NMOS transistor.

8. The erasable programmable non-volatile memory cell according to claim 1 wherein the cell is formed in an N type ion well, the first select gate transistor, the first floating gate transistor, second select gate transistor and second floating gate transistor are PMOS transistors.

9. The erasable programmable non-volatile memory cell according to claim 1 wherein the drain of the second floating gate transistor is electrically connected to a first bit line, while the drain of the first floating gate transistor is electrically connected to a second bit line.

10. The erasable programmable non-volatile memory cell according to claim 2 wherein when programming or reading the EPROM cell, the ion well is coupled to V_SS.

11. The erasable programmable non-volatile memory cell according to claim 1 wherein when programming or reading the EPROM cell, the source line is coupled to V_SS.

12. The erasable programmable non-volatile memory cell according to claim 1 wherein when programming or reading the EPROM cell, the select gates are coupled to a select gate voltage to turn on the channel thereof.

13. The erasable programmable non-volatile memory cell according to claim 9 wherein when programming the EPROM cell, a first bit line voltage (V_BL1) is applied to the first bit line while the second bit line is floating, and such assignment of operating voltages are interchangeable between the first bit line and the second bit line.

14. The erasable programmable non-volatile memory cell according to claim 13 wherein the first bit line voltage is negative when applying to a PMOS transistor, and is positive when applying to an NMOS transistor.

15. The erasable programmable non-volatile memory cell according to claim 13 wherein the first bit line voltage'"'"'s absolute value ranges between 3 V and 10 V.

16. A non-volatile memory cell comprising a first transistor and a second transistor sharing one floating gate strip, wherein source/drain of the first and second transistors are connected out to independent four terminals, and wherein when programming the non-volatile memory cell, drain of the first transistor is biased to VPP, source of the first transistor is biased to VSS1, drain of the second transistor is floated, and source of the second transistor is biased to VSS2.

17. The non-volatile memory cell according to claim 16 wherein the four terminals include a source terminal that is serially connected to a switch device for selection of the non-volatile memory cell.

18. The non-volatile memory cell according to claim 17 wherein the said switch device is a metal-oxide-semiconductor (MOS) transistor.

19. The non-volatile memory cell according to claim 17 wherein the said switch device comprises two MOS transistors sharing a gate, wherein a first MOS transistor of the switch device has a drain that is connected to the source of the first transistor of the said non-volatile memory cell, while a second MOS transistor of the switch device has a drain that is connected to the source of the second transistor of the said non-volatile memory cell.

20. The non-volatile memory cell according to claim 16 wherein the said transistors are MOS transistors.