Automatic operand load and store

• US 20060026391A1
• Filed: 07/25/2005
• Published: 02/02/2006
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cabillic, Gilbert, Chauvel, Gerard, Lesot, Jean-Philippe
• Granted Patent: US 7,493,476 B2
• Time in Patent Office: Days
• US Class Current: 712/209
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor that comprises decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, the single instruction requiring an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit and stores the operand to the second storage unit for use by the group of instructions.

Claims

1. A processor, comprising:

decode logic coupled to a first storage unit and comprising a data structure; and

a second storage unit coupled to said decode logic;

wherein the decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in said data structure, processes a group of instructions in lieu of the single instruction, the single instruction requiring an operand;

wherein, if indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit and stores the operand to the second storage unit for use by said group of instructions.

2. The processor of claim 1, wherein a size of the operand is indicated by bits in the data structure.

3. The processor of claim 1, wherein a size of the operand is selected from the group consisting of one byte, two bytes and four bytes.

4. The processor of claim 1, wherein the decode logic obtains and stores the operand before the group of instructions is executed.

5. The processor of claim 1, wherein the first storage unit comprises an instruction cache and the second storage unit comprises a register.

6. The processor of claim 1, wherein the second storage unit is a dedicated register.

7. The processor of claim 1, wherein a program counter is incremented according to a size of the operand, said program counter used by the decode logic when processing instructions.

8. The processor of claim 1, wherein the operand is stored with the single instruction in the first storage unit.

9. An electronic device, comprising:

decode logic coupled to a first storage unit and a second storage unit; and

a data structure comprising a plurality of entries, at least one entry having a corresponding instruction and comprising;

a first field indicating whether a group of instructions is to be processed in lieu of the corresponding instruction; and

a second field indicating a size of an operand required by the corresponding instruction;

wherein the decode logic obtains the operand from the first storage unit using the second field and stores the operand to the second storage unit for use by said group of instructions.

10. The electronic device of claim 9, wherein the electronic device is selected from the group consisting of a battery-operated device and a wireless communication device.

11. The electronic device of claim 9, wherein the size of the operand is selected from the group consisting of one byte, two bytes and four bytes.

12. The electronic device of claim 9, wherein the second field indicates that the size of the operand is zero bytes.

13. The electronic device of claim 9, wherein a program counter used by the decode logic to process instructions is incremented based on the size of the operand.

14. The electronic device of claim 9, wherein the decode logic stores the operand before the group of instructions is executed.

15. The electronic device of claim 9, wherein the second storage unit is a dedicated register.

16. The electronic device of claim 9, wherein the first storage unit comprises a cache and the second storage unit comprises a register.

17. A method, comprising:

fetching a single instruction using a decode logic that comprises a data structure, said decode logic coupled to a first storage unit and a second storage unit, said single instruction requiring an operand;

if indicated by a first field in the data structure, processing a group of instructions in lieu of the single instruction;

obtaining the operand from the first storage unit, a size of the operand indicated by a second field in the data structure; and

storing the operand in the second storage unit for use by the group of instructions.

18. The method of claim 17, wherein the size of the operand is selected from the group consisting of one byte, two bytes and four bytes.

19. The method of claim 17, wherein storing the operand comprises storing the operand before the group of instructions is executed.

20. The method of claim 17, wherein storing the operand in the second storage unit comprises storing the operand in a dedicated register.

21. The method of claim 17 further comprising executing the group of instructions, wherein the at least one of said group of instructions causes the operand stored in the second storage unit to be accessed.