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• US 20060026403A1
• Filed: 07/25/2005
• Published: 02/02/2006
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chauvel, Gerard
• Granted Patent: US 8,024,554 B2
• Time in Patent Office: Days
• US Class Current: 712/226
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor comprising fetch logic adapted to fetch instructions from memory and decode logic coupled to the fetch logic and adapted to decode the fetched instructions. If a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or more instructions is executed in lieu of the particular fetched instruction. If the bit is in a second state, both the group and the particular fetched instruction are executed.

Claims

1. A processor, comprising:

fetch logic adapted to fetch instructions from memory; and

decode logic coupled to said fetch logic and adapted to decode said fetched instructions;

wherein, if a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or more instructions is executed in lieu of the particular fetched instruction;

wherein, if the bit is in a second state, both said group and the particular fetched instruction are executed.

2. The processor of claim 1, wherein execution of said group causes the processor to modify a counter by decrementing a register initialized to a predetermined threshold value.

3. The processor of claim 2, wherein the particular fetched instruction is modified after the counter reaches or exceeds a predetermined threshold.

4. The processor of claim 1, wherein the particular fetched instruction and the group are executed using different program counters.

5. The processor of claim 1, wherein, if the bit is in the second state, a status of a flag is modified when the group is executed so that, during a next iteration, the particular fetched instruction is executed and the group is not executed.

6. The processor of claim 5, wherein the status of the flag is adjusted when the particular fetched instruction is executed so that, during a subsequent iteration, at least the group is executed.

7. The processor of claim 5, wherein, prior to servicing an interrupt request, the processor stores the status of the flag so that the status of the flag is available to the processor after servicing the interrupt request.

8. An electronic device, comprising:

a decode logic adapted to decode instructions from an instruction storage unit, said decode logic comprising a data structure;

wherein the data structure comprises a plurality of entries, each entry corresponding to a separate instruction and associated with;

a first bit indicating whether the corresponding instruction is to be replaced by a micro-sequence comprising one or more secondary instructions; and

a second bit indicating whether the micro-sequence is to be executed alone or in addition to the corresponding instruction.

9. The electronic device of claim 8, wherein the corresponding instruction and the one or more secondary instructions are processed using different program counters.

10. The electronic device of claim 8, wherein the electronic device is selected from the group consisting of battery-operated devices and wireless communication devices.

11. The electronic device of claim 8, wherein the micro-sequence modifies a counter, and wherein the corresponding instruction is executed when the counter is modified.

12. The electronic device of claim 11, wherein the corresponding instruction is modified when the counter meets or exceeds a predetermined threshold value.

13. The electronic device of claim 12, wherein at least one of the first bit and the second bit is modified when the counter meets or exceeds the predetermined threshold value.

14. The electronic device of claim 11, wherein the counter is modified by decrementing a register initialized to a predetermined threshold value.

15. A method, comprising:

if a bit in a processor is in a first state, executing a group comprising one or more secondary instructions in lieu of a primary instruction; and

if the bit is in a second state, executing both the group and the primary instruction.

16. The method of claim 15 wherein, if the bit is in the second state, the primary instruction is executed after the group is executed.

17. The method of claim 16, further comprising asserting a flag when executing the group such that the primary instruction is executed during a subsequent iteration and the group is not executed during said subsequent iteration.

18. The method of claim 15, wherein, when executed, the group causes a counter to be modified.

19. The method of claim 18, wherein modifying the counter comprises either incrementing or decrementing a register.

20. The method of claim 19, wherein decrementing the register comprises decrementing a register initialized to a predetermined threshold value.

21. The method of claim 18 further comprising modifying the primary instruction when the counter meets or exceeds a predetermined threshold value.