Reduced-step CMOS processes for low-cost radio frequency identification devices

• US 20060033167A1
• Filed: 08/11/2004
• Published: 02/16/2006
• Est. Priority Date: 08/11/2004
• Status: Active Grant

• Current Assignee: Maurice Bailey
• Original Assignee: Identifi Technologies Incorporated
• Inventors: Novosel, David
• Granted Patent: US 7,772,063 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects

Abstract

Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the number and complexity of required process steps, thereby reducing the cost for manufacturing ICs. By recognizing the particular needs for low-cost integrated circuits such as RFID devices (for example, reduced needs for performance, power and longevity) and by identifying a reduced set of CMOS process steps, an advantageous solution is achieved for producing low-cost integrated circuits and low-cost RFID devices.

Claims

1. A method for CMOS processing of low-cost integrated circuits, comprising:

forming first-type well regions within a second-type semiconductor substrate;

creating second-type MOS transistors within the first-type well regions and first-type MOS transistors within the substrate without utilizing a lightly doped drain (LDD) process; and

providing interconnect circuitry utilizing polysilicon layers without utilizing a silicide or salicide process and utilizing two or fewer metal interconnect layers.

2. The method of claim 1, wherein the first-type is N-type, the second-type is P-type, the first-type MOS transistors are NMOS transistors, and the second-type MOS transistors are PMOS transistors.

3. The method of claim 2, further comprising controlling threshold voltages for the NMOS transistors with a processing step directed to the channel of the NMOS transistors, and allowing the controlling step to apply to the channels of the PMOS transistors as well, thereby allowing threshold voltages for the PMOS transistors to vary.

4. The method of claim 1, wherein the first-type is P-type, the second-type is N-type, the first-type MOS transistors are PMOS transistors, and the second-type MOS transistors are NMOS transistors.

5. The method of claim 4, further comprising controlling threshold voltages for the PMOS transistors with a processing step directed to the channel of the PMOS transistors, and allowing the controlling step to apply to the channels of the NMOS transistors as well, thereby allowing threshold voltages for the NMOS transistors to vary.

6. The method of claim 1, wherein the CMOS process has a minimum device geometry of 1.0 microns or less.

7. The method of claim 1, wherein the CMOS process has a minimum device geometry of 0.5 microns or less.

8. The method of claim 1, further comprising fabricating an integrated radio frequency identification (RFID) device.

9. The method of claim 8, wherein the providing interconnect circuitry step is carried out without utilizing metal plugs to fill contact holes.

10. The method of claim 8, wherein the providing interconnect circuitry step is carried out without performing a chemical mechanical polishing (CMP) processing step.

11. The method of claim 8, wherein the first-type MOS and the second-type MOS transistors are not separated by a field implant.

12. The method of claim 8, further comprising forming embedded memory within the RFID device.

13. The method of claim 12, wherein the embedded memory comprises non-volatile memory.

14. The method of claim 8, further comprising integrating an antenna with the integrated RFID device.

15. The method of claim 8, wherein the fabrication is completed with 9 or fewer masks.

16. The method of claim 15, wherein the process steps consists essentially of an N-well definition step, an active area definition step, a polysilicon patterning step, a source/drain implantation step, a contact definition step, a metal one patterning step, a via definition step, and a metal two patterning step.

17. The method of claim 15, wherein the process steps consists essentially of an N-well definition step, an active area definition step, a polysilicon patterning step, a source/drain implantation step, a contact definition step, a metal one patterning step, a via definition step, a metal two patterning step, and a passivation step.

18. The method of claim 8, wherein the RFID device does not include electrostatic discharge (ESD) protection circuitry.

19. The method of claim 1, wherein the substrate of a starting wafer does not include a lightly doped epitaxial (EPI) layer.

20. The method of claim 8, wherein the first-type MOS and the second-type MOS transistors are not separated by a field implant;

wherein the providing interconnect circuitry step is carried out without performing a chemical mechanical polishing (CMP) processing step;

wherein the RFID device does not include electrostatic discharge (ESD) protection circuitry; and

wherein the substrate of a starting wafer does not include a lightly doped epitaxial (EPI) layer.

21. A low-cost CMOS integrated circuit, comprising:

first-type MOS transistors formed within a second-type semiconductor substrate without utilizing a lightly doped drain (LDD) process;

second-type MOS transistors formed in first-type well regions within the substrate without utilizing a LDD process; and

interconnect circuitry comprising non-silicide and non-salicide polysilicon layers and two or fewer metal interconnect layers.

22. The low-cost CMOS integrated circuit of claim 21, wherein the first-type is N-type, the second-type is P-type, the first-type MOS transistors are NMOS transistors, and the second-type MOS transistors are PMOS transistors.

23. The low-cost CMOS integrated circuit of claim 22, wherein the NMOS transistors have controlled threshold voltages and the PMOS transistors have varied threshold voltages.

24. The low-cost CMOS integrated circuit of claim 21, wherein the first-type is P-type, the second-type is N-type, the first-type MOS transistors are PMOS transistors, and the second-type MOS transistors are NMOS transistors.

25. The low-cost CMOS integrated circuit of claim 24, wherein the NMOS transistors have controlled threshold voltages and the PMOS transistors have varied threshold voltages

26. The low-cost CMOS integrated circuit of claim 21, wherein the integrated circuit has a minimum device geometry of 1.0 microns or less.

27. The low-cost CMOS integrated circuit of claim 21, wherein the integrated circuit has a minimum device geometry of 0.5 microns or less.

28. The low-cost CMOS integrated circuit of claim 21, wherein the integrated circuit comprises an integrated radio frequency identification (RFID) device.

29. The low-cost CMOS integrated circuit of claim 28, wherein the interconnect circuitry for the integrated circuit was formed without utilizing metal plugs to fill contact holes.

30. The low-cost CMOS integrated circuit of claim 28, wherein the interconnect circuitry for the integrated circuit was formed without utilizing a Chemical Mechanical Polishing (CMP) process step.

31. The low-cost CMOS integrated circuit of claim 28, wherein the first-type MOS and the second-type MOS transistors are not separated by a field implant.

32. The low-cost CMOS integrated circuit of claim 28, further comprising embedded memory within the RFID device.

33. The low-cost CMOS integrated circuit of claim 32, wherein the embedded memory comprises non-volatile memory.

34. The low-cost CMOS integrated circuit of claim 28, further comprising an antenna integrated with the RFID device.

35. The low-cost CMOS integrated circuit of claim 28, wherein the RFID device does not include electrostatic discharge (ESD) protection circuitry.

36. The low-cost CMOS integrated circuit of claim 21, wherein the substrate does not include a lightly doped epitaxial (EPI) layer.

37. The low-cost CMOS integrated circuit of claim 28, wherein the RFID device further comprises power circuitry, receive path circuitry, transmit path circuitry and logic circuitry.

38. The low-cost CMOS integrated circuit of claim 37, wherein the RFID device costs five cents or fewer to fabricate.

39. The low-cost CMOS integrated circuit of claim 37, wherein the circuitry is configured at least in part to account for the varied threshold voltages for the second-type MOS transistors.

40. The low-cost CMOS integrated circuit of claim 28, wherein the first-type MOS and the second-type MOS transistors are not separated by a field implant, wherein the interconnect circuitry for the integrated circuit was formed without utilizing a Chemical Mechanical Polishing (CMP) process step, wherein the RFID device does not include electrostatic discharge (ESD) protection circuitry, and wherein the substrate does not include a lightly doped epitaxial (EPI) layer.

41. A method for CMOS processing of low-cost integrated circuits, comprising:

forming first-type well regions within a second-type semiconductor substrate;

creating second-type MOS transistors within the first-type well regions and first-type MOS transistors within the substrate; and

providing interconnect circuitry;

wherein the method further comprises one or more of the following process features;

creating second-type MOS transistors within the first-type well regions and first-type MOS transistors within the substrate without utilizing a lightly doped drain (LDD) process;

providing interconnect circuitry utilizing polysilicon layers without utilizing a silicide or salicide process and utilizing two or fewer metal interconnect layers;

controlling threshold voltages for the first-type MOS transistors with a processing step directed to the channel of the first-type MOS transistors, and allowing the controlling step to apply to the channels of the second-type MOS transistors as well, thereby allowing threshold voltages for the second-type MOS transistors to vary;

creating the first-type MOS and the second-type MOS transistors such that they are not separated by a field implant;

providing the interconnect circuitry without performing a chemical mechanical polishing (CMP) processing step;

providing the interconnect circuitry without utilizing metal plugs to fill contact holes;

providing a resulting integrated circuit that does not include electrostatic discharge (ESD) protection circuitry; and

utilizing a starting wafer having a substrate lacking a lightly doped epitaxial (EPI) layer.

42. The method of claim 41, wherein the first-type is N-type, the second-type is P-type, the first-type MOS transistors are NMOS transistors, and the second-type MOS transistors are PMOS transistors.

43. The method of claim 41, wherein the first-type is P-type, the second-type is N-type, the first-type MOS transistors are PMOS transistors, and the second-type MOS transistors are NMOS transistors.

44. The method of claim 41, further comprising fabricating an integrated radio frequency identification (RFID) device.

45. The method of claim 44, wherein the CMOS process has a minimum device geometry of 1.0 microns or less.

46. The method of claim 44, wherein the CMOS process has a minimum device geometry of 0.5 microns or less.