Non-volatile semiconductor memory device and semiconductor memory device

• US 20060034142A1
• Filed: 08/02/2005
• Published: 02/16/2006
• Est. Priority Date: 08/13/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Uchiyama, Tomohiro, Ooishi, Tsukasa, Miyazaki, Shinya
• Granted Patent: US 7,286,416 B2
• Time in Patent Office: Days
• US Class Current: 365/230.60
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 8/10 Decoders

Abstract

For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.

Claims

1. A non-volatile semiconductor memory device, comprising:

a memory array having a plurality of non-volatile memory cells, arranged in rows and columns, each for storing data in a non-volatile manner;

predecode circuitry arranged along one side of said memory array, for predecoding an address signal designating a memory cell of said memory array, and generating a predecoded address signal;

address latch circuitry arranged along the one side of said memory array corresponding to said predecode circuitry, for latching the predecoded address signal from said predecode circuitry;

cell selecting circuitry responsive to latching of the address of said address latch circuitry, for selecting an addressed memory cell of said memory array in accordance with the latched predecoded address signal latched by said address latch circuitry; and

data reading circuitry for reading, in a data reading mode, data of the memory cell selected by said cell selecting circuitry.

2. The non-volatile semiconductor memory device according to claim 1, wherein

said memory array is divided into a plurality of blocks;

said address latch circuitry includes a plurality of address latch circuits arranged corresponding to respective blocks; and

said cell selecting circuitry includes a plurality of decode circuits, arranged corresponding to the blocks, each for decoding the address signal from the address latch circuit arranged for the corresponding block and generating a cell selection signal, with interconnections between said plurality of address latch circuits and corresponding decode circuits being made equal in length to each other.

3. The non-volatile semiconductor memory device according to claim 2, wherein

said predecode circuitry includes a plurality of predecode circuits arranged corresponding to the blocks, and an output signal of each of said predecode circuits is applied to a corresponding address latch circuit.

4. The non-volatile semiconductor memory device according to claim 1, wherein

said cell circuitry includes

an X decode circuit for decoding an X address signal designating a row received from said address latch circuitry and generating a row selection signal, and

a Y decode circuit for decoding a Y address signal designating a column received from said address latch circuitry and generating a column selection signal.

5. The non-volatile semiconductor memory device according to claim 1, wherein

said cell selecting circuitry resets said address latch circuitry to an initial state, after a memory cell is selected.

6. The non-volatile semiconductor memory device according to claim 5, wherein

said cell selecting circuitry further resets an internal state of said cell selecting circuitry to an initial state, after said memory cell is selected.

7. The non-volatile semiconductor memory device according to claim 5, wherein

said data reading circuitry includes a sense amplifier circuit for amplifying data of said selected memory cell to generate an internal read data;

and

said cell selecting circuitry resets said address latch circuitry in response to a signal controlling activation of said sense amplifier circuit.

8. A semiconductor memory device, comprising:

a memory array having a plurality of memory cells arranged in of rows and columns;

address latch circuitry for latching an address signal designating a memory cell of said memory array;

cell selecting circuitry for selecting an addressed memory cell of said memory array in accordance with a latched address signal of said address latch circuitry, said cell selecting circuitry resetting said address latch circuitry to an initial state after selection of said memory cell in a data read mode of operation; and

data reading circuitry for reading data of the memory cell selected by said cell selecting circuitry for generating an internal data in said data read mode of operation.

9. The semiconductor memory device according to claim 8, wherein

said cell selecting circuitry resets said cell selecting circuitry concurrently with the resetting of said address latch circuitry, after the selection of said memory cell.

10. The semiconductor memory device according to claim 8, wherein

said cell selecting circuitry stops an operation of said resetting, when a test mode is set.

11. The semiconductor memory device according to claim 8, further comprising:

a data output circuit for generating an internal output data from the internal data received from said data reading circuitry; and

an output control circuit for monitoring a state of data reading from said data reading circuitry, and resetting said data output circuit in accordance with the monitored state.

12. The semiconductor memory device according to claim 11, wherein

said data output circuit includes a data latch circuit for latching the internal data received from said data reading circuitry;

and

said data output control circuit resets said data output circuit in response to a monitor signal generated in accordance with an activating signal controlling activation of said data reading circuitry.

13. The semiconductor memory device according to claim 11, wherein

said output control circuit receives a monitor signal through a signal line providing a signal propagation delay corresponding to signal propagation delay of a signal propagation path from said data reading circuitry to said data output circuit, and resets said data output circuit in accordance with the received monitor signal, said monitor signal being generated in correspondence to an activating signal activating said data reading circuitry.

14. A semiconductor memory device, comprising:

a memory array divided into a plurality of memory mats each having a plurality of memory cells, said plurality of memory mats being subject to concurrent memory cell selection and data reading in a data reading mode of operation, and each memory mat including a data region for storing bits of data, and an error correction bit region for storing parity bits forming an error correction code for the data.

15. The semiconductor memory device according to claim 14, wherein

parity bits for the error correction code for one multi-bit data are stored dispersed uniformly over said plurality of memory mats.