Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure

• US 20060043461A1
• Filed: 10/25/2005
• Published: 03/02/2006
• Est. Priority Date: 11/20/2002
• Status: Active Grant

• Current Assignee: Numonyx BV (Micron Technology, Inc.)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Zuliani, Paola, Palumbo, Elisabetta, Annunziata, Roberto, Scaravaggi, Marina
• Granted Patent: US 7,456,467 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps: defining on a same semiconductor substrate respective active areas for the byte selection transistor, for the floating gate transistor and for the selection transistor split by portions of insulating layer; depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer on the whole substrate and a second polysilicon layer, characterised in that it comprises the following steps: removing through a traditional photolithographic technique the multilayer structure to form at least a couple of two bands developing substantially in a parallel way to the columns of the matrix of memory cells, the first band being effective to define the gate regions of the byte selection transistor and of the selection transistor, the second band being effective to define the gate region of the floating gate transistor, a portion of the first band further extending on the portion of insulating layer which is adjacent to the byte selection transistor, forming an opening in the portion up to expose the first polysilicon layer, forming a conductive layer in the opening to put said first polysilicon layer in electric contact with said second polysilicon layer.

Claims

1. A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps:

defining on a semiconductor substrate one or more active areas for said byte selection transistor, for said floating gate transistor and for said selection transistor, the active areas having portions of an insulating layer adjacent thereto;

depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer and a second polysilicon layer;

removing through a photolithographic technique said multilayer structure to form at least two bands, the first band being effective to define the gate regions of said byte selection transistor and of said selection transistor, the second band being effective to define the gate region of said floating gate transistor, a portion of said first band further extending on the portion of insulating layer which is adjacent to said byte selection transistor,

forming an opening in said portion to expose said first polysilicon layer,

forming a conductive layer in said opening to put said first polysilicon layer in electrical contact with said second polysilicon layer.

2. The process for manufacturing a byte selection transistor according to claim 1 wherein said portion that extends over the insulating layer has a greater width than the width of the gate regions of single transistors.

3. The process for manufacturing a byte selection transistor according to claim 1 wherein said conductive layer is a polysilicon layer.

4. The process for manufacturing a byte selection transistor according to claim 1 wherein said conductive layer is a metallization layer.

5. The process for manufacturing a byte selection transistor according to claim 1, including:

forming a silicide layer on said second polysilicon layer and on the portion of said first polysilicon layer exposed through said opening.

6. A circuit structure comprising:

a semiconductor substrate; and

a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, the substrate having thereon circuitry comprising high and low voltage transistors, each memory cell comprising a floating gate transistor and a selection transistor, said rows being interrupted by at least a couple of byte selection transistors, said transistors being manufactured in respective active areas delimited by portions of an insulating layer, said circuit structure having a first and a second multilayer band formed on said semiconductor substrate, each band having a first gate oxide layer, a first polysilicon layer, a second dielectric layer and a second polysilicon layer, said first band defining the gate regions of said byte selection transistor and of said selection transistor in correspondence with said respective active areas and having a portion extending on a portion of the insulating layer adjacent to said byte selection transistor, said second band defining the gate regions of said floating gate transistor, said portion being provided with an opening, formed in said second dielectric layer and in said second polysilicon layer, filled at least partially by a conductive layer.

7. The circuit structure according to claim 6 wherein said portion has a greater width at the location of said opening than the width at the location of said active areas.

8. The circuit structure according to claim 6, characterised in that said conductive layer is a polysilicon layer.

9. The circuit structure according to claim 6 wherein said conductive layer is a metallization layer.