Method and apparatus for remotely buffering test channels

• US 20060049820A1
• Filed: 09/09/2004
• Published: 03/09/2006
• Est. Priority Date: 09/09/2004
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A.
• Granted Patent: US 7,453,258 B2
• Time in Patent Office: Days
• US Class Current: 324/754.70
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test

Abstract

A system is provided to enable leakage current measurement or parametric tests to be performed with an isolation buffer provided in a channel line. Multiple such isolation buffers are used to connect a single signal channel to multiple lines. Leakage current measurement is provided by providing a buffer bypass element, such as a resistor or transmission gate, between the input and output of each buffer. The buffer bypass element can be used to calibrate buffer delay out of the test system by using TDR measurements to determine the buffer delay based on reflected pulses through the buffer bypass element. Buffer delay can likewise be calibrated out by comparing measurements of a buffered and non-buffered channel line, or by measuring a device having a known delay.

Claims

1. An apparatus comprising:

an isolation buffer provided in a test channel of a test system; and

a buffer bypass element provided in the test channel between a signal input and output of the isolation buffer.

2. The apparatus of claim 1, wherein the buffer bypass element comprises a resistor.

3. The apparatus of claim 1, wherein the buffer bypass element comprises a transmission gate.

4. The apparatus of claim 3, wherein the isolation buffer is a tristate buffer.

5. The apparatus of claim 3, wherein a signal is provided to disable the transmission gate when the tristate buffer is enabled and to enable the transmission gate when the tristate buffer is disabled.

6. The apparatus of claim 1, wherein the buffer bypass element comprises a transistor.

7. The apparatus of claim 6, wherein the transistor is a CMOS device having a source-drain path connected between the input and output of the isolation buffer.

8. A probe card comprising:

isolation buffers provided in test channels; and

buffer bypass elements provided in parallel with the isolation buffers.

9. The probe card of claim 8, wherein the test channels are each terminated in a probe contact.

10. The probe card of claim 9, wherein the probe contacts comprise resilient springs.

11. The apparatus of claim 8, wherein the buffer bypass elements comprise resistors.

12. The apparatus of claim 8, wherein the buffer bypass elements comprise transmission gates.

13. An apparatus comprising:

a circuit having branches from a common node;

isolation buffers, each isolation buffer provided in one of the branches; and

buffer bypass elements, each buffer bypass element provided between an input and output of one of the isolation buffers.

14. The apparatus of claim 13, further comprising an additional buffer provided in a signal line path connected to the common node, the additional buffer having an input connected to the inputs of the isolation buffers, wherein the buffer bypass elements are provided between the input of the additional buffer and the outputs of each of the isolation buffers.

15. The apparatus of claim 13, wherein the buffer bypass elements comprise resistors.

16. The apparatus of claim 13, wherein the buffer bypass elements comprise transmission gates.

17. The apparatus of claim 16, wherein the additional buffer comprises a tristate buffer.

18. The apparatus of claim 17, wherein a signal is provided to disable the transmission gates when the tristate buffer is enabled and to enable the transmission gates when the tristate buffer is disabled.

19. The apparatus of claim 13, further comprising additional buffers, each additional buffer provided in series in each branch with one of the isolation buffers, wherein the buffer bypass elements are provided in parallel with the series buffers in each branch.

20. The apparatus of claim 13, further comprising:

a delay control circuit having an output providing a variable delay control input to the isolation buffers, the delay control circuit setting a delay control voltage potential at its output to control delay through the isolation buffers to substantially match delay through a time delay reference.

21. A method of measuring the delay of a buffer in a test circuit, the method comprising:

providing a signal pulse through the buffer;

measuring the signal pulse as reflected from a buffer bypass element provided between an input and output of the buffer; and

determining the delay introduced by the buffer from the reflected signal pulse using a time domain reflectometer calculation.

22. The method of claim 21, wherein the buffer output is connected to a test probe.

23. A method of measuring the delay of a buffer in a test circuit, wherein the buffer is provided in a first transmission line, the method comprising:

measuring delay of the first transmission line and the buffer;

measuring delay of a second transmission line substantially similar to the first transmission line without a buffer; and

calculating the delay through the buffer by determining a difference between a delay through the first transmission line with the buffer and the delay through the second transmission line.

24. The method of claim 23, wherein a buffer bypass element is provided between an input and an output of the buffer.

25. A method of calibrating out a delay of a buffer in a test circuit, the method comprising:

measuring a delay of a device having a known delay using the test device with the buffer; and

calibrating out the delay of the buffer by comparing the measured delay of the device with the known delay.

26. The method of claim 25, wherein a buffer bypass element is provided between an input and an output of the buffer.