Slave device having independent error recovery

• US 20060053331A1
• Filed: 09/03/2004
• Published: 03/09/2006
• Est. Priority Date: 09/03/2004
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Li, Whitney, Chou, Norman C.
• Granted Patent: US 7,526,676 B2
• Time in Patent Office: Days
• US Class Current: 714/2
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1471 involving logging of persistent data for recovery

Abstract

A slave device adapted to couple to a master processor and including an error handler and a communication controller. The error handler is configured to detect errors internal to the slave device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detected error and to initiate and perform the selected error recovery operation. The communication controller is configured to communicate with the master processor according to a master/slave protocol, and configured to maintain the master/slave protocol during performance of the selected error recovery operation by the error handler.

Claims

1. A slave device adapted to couple to a master processor, the slave device comprising:

an error handler configured to detect errors internal to the slave device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detected error and configured to initiate and perform the selected error recovery operation; and

a communication controller configured to communicate with the master processor according to a master/slave protocol, and configured to maintain the master/slave protocol during performance of the selected error recovery operation by the error handler.

2. The slave device of claim 1, wherein the error handler is configured to detect a plurality of types of error and to select the desired error recovery operation from a plurality of error recovery operations based on the type of error detected.

3. The slave device of claim 1, wherein the communication controller provides to the master processor a reset signal indicating when a selected error recovery operation which was initiated while communication controller was communicating with the master processor, the reset signal instructing the master processor to perform a check-point retry operation.

4. The slave device of claim 1, wherein the communication controller is configured to perform data transactions with the master processor according to the master/slave protocol, each transaction comprising a predetermined amount of data, and wherein the communication controller is configured to complete a transaction on-going with the master processor when the error handler initiates the selected error recovery operation.

5. The slave device of claim 4, wherein the communication controller is configured to fabricate an amount of data necessary to complete a data transaction on-going from the slave device to the master processor after the error handler initiates the selected error recovery operation, wherein the amount of fabricated data comprises a difference between the predetermined amount of data and an amount of data received by the master processor from the slave device prior to the initiation of the selected error recovery operation.

6. A packet routing device comprising:

an error handler configured to detect errors internal to the packet routing device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detected error, and configured to initiate and perform the selected error recovery operation; and

a communication controller adapted to couple to a master processor and to a network fabric, the communication controller configured to transfer data packets between the master processor and the network fabric according to a communication protocol, and configured to maintain the communication protocol during performance of the selected error recovery operation by the error handler.

7. The packet routing device of claim 6, wherein the communication controller is configured to transfer data packets between the master processor and the packet routing device through at a series of data transactions according to the communication protocol, each data transaction comprising a predetermined amount of data, and wherein the communication controller is configured to complete a data transaction on-going with the master processor when the error handler initiates the selected error recovery operation to thereby maintain the master/slave protocol.

8. The packet routing device of claim 7, wherein the communication controller is configured to provide a fabricated amount of data necessary to complete a data transaction on-going from the packet routing device to the master processor after the error handler initiates the selected error recovery operation, wherein the amount of fabricated data comprises a difference between the predetermined amount of data and an amount of data received by the master processor from the packet routing device prior to the initiation of the selected error recovery operation.

9. The packet routing device of claim 7, wherein the communication controller is configured to provide a reset signal to the master processor after completion of a selected error recovery operation which was initiated while a data transaction was on-going between the communication controller and the master processor, wherein the reset signal instructs the master processor to perform a check-point retry.

10. The packet routing device of claim 6, wherein the communication controller further comprises:

a blocking mechanism, wherein the communication controller sets the blocking mechanism to prevent potentially corrupted data packets from being transferred from the packet routing device to the network fabric when the selected error recovery operation is initiated while the communication controller is transferring data between the packet routing device and the master processor.

11. The packet routing device of claim 10, wherein the blocking mechanism is configured to be reset by the master processor.

12. The packet routing device of claim 10, wherein the blocking mechanism comprises a semaphore.

13. A memory device comprising:

an error handler configured to detect errors internal to the memory device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detected error, and configured to initiate and perform the selected error recovery operation;

a storage medium configured to store data; and

a memory controller adapted to couple to a master processor, the memory controller configured to perform data transactions between the master processor and the storage medium according to a communication protocol and configured to maintain the communication protocol during performance of the selected error recovery operation by the error handler.

14. The memory device of claim 13, wherein each data transaction comprises a predetermined amount of data, and wherein the memory controller is configured to complete a data transaction on-going between the memory device and master processor when the error handler initiates the selected error recovery to thereby maintain the communication protocol.

15. The memory device of claim 13, wherein the memory device further comprises:

a blocking mechanism, wherein the memory controller sets the blocking mechanism to prevent potentially corrupted data from being written to the storage medium when the selected error recovery operation is initiated while a data transaction is on-going from the master processor to the memory device.

16. The memory device of claim 15, wherein the storage medium comprises a write-once type storage medium.

17. The memory device of claim 13, wherein the memory controller is configured to provide a reset signal to the master processor after completion of a selected error recovery operation which was initiated while a data transaction was ongoing between the memory device and the master processor, wherein the reset signal instructs the master processor to perform a checkpoint retry.

18. A network system comprising:

a master processor; and

a slave device coupled to the master processor, the slave device comprising;

an error handler configured to detect errors internal to the slave device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detect error and configured to initiate and perform the selected error recovery operation; and

a communication controller configured to communicate with the master processor according to a master/slave protocol, and configured to maintain the master/slave protocol during performance of the selected error recovery operation by the error handler.

19. The network system of claim 18, wherein the communication controller is configured to perform data transactions with the master processor according to the master/slave protocol, each transaction comprising a predetermined amount of data, and wherein the communication controller is configured to complete a transaction on-going with the master processor when the error handler initiates the selected error recovery operation to thereby maintain the master/slave protocol.

20. The network system of claim 18, wherein the communication controller provides to the master processor a reset signal indicating when a selected error recovery operation which was initiated while communication controller was communicating with the master processor, and wherein the master processor is configured to perform a checkpoint retry in response to the reset signal.

21. A method of operating a slave device adapted to couple to a master processor, the method comprising:

communicating with the master processor according to a master/slave protocol;

detecting at least one error internal to the slave device;

selecting an error recovery operation based on the at least one detected internal error;

initiating and performing the selected error recovery operation independent of the master processor; and

maintaining the master/slave protocol with the master processor during performance of the selected error recovery operation.

22. The method of claim 21, wherein communicating with the master processor further comprises:

performing data transactions with the master processor according to the master/slave protocol, each transaction comprising a predetermined amount of data.

23. The method of claim 22, wherein maintaining the master/slave protocol further comprises:

completing a data transaction on-going with the master processor when the selected error recovery operation is initiated.

24. The method of claim 22, wherein completing a data transaction further comprises:

fabricating an amount of data necessary to complete an on-going data transaction from the slave device to the master processor after initiation of the selected error recovery operation, wherein the amount of fabricated data comprises a difference between the predetermined amount of data and an amount of data received by the master processor from the slave device as part of the on-going data transaction prior to the initiation of the selected error recovery operation.