Digital controller for high-frequency switching power supplies

• US 20060055574A1
• Filed: 12/09/2002
• Published: 03/16/2006
• Est. Priority Date: 11/09/2001
• Status: Active Grant

• Current Assignee: Imperial Chemical Industries Limited (Nouryon BV)
• Original Assignee: Imperial Chemical Industries Limited (Nouryon BV)
• Inventors: Maksimovic, Dragan, Prodic, Aleksandar, Patella, Benjamin James, Dhar, Sandeep Chaman
• Granted Patent: US 7,595,686 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H03M 1/502 using tapped delay lines
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses

Abstract

A voltage controller (150), the controller comprising: a voltage comparator (700) operative to provide a digital error signal (152); a compensator (300) operative to determine a digital control signal (154) based on said provided error signal; and a modulator (400) operative to provide a power control signal (156) based on said determined digital control signal, wherein said comparator, said compensator, and said modulator are implemented entirely with digital logic gates.

Claims

1. A voltage controller comprising

a compensator, including a lookup table for determining a digital control signal based on a digital error signal;

a modulator operative to provide a power control signal in response to said determined digital control signal; and

a delay line analog to digital converter operative to compare a converter voltage to a reference voltage and generate said digital error signal indicative of a difference between said compared voltages.

2. The controller of claim 1 wherein said controller includes no passive electronic components.

3. The controller of claim 1 wherein said comparator is implemented entirely with digital logic gates.

4. The controller of claim 1 wherein all energy-storing components in said controller are digital logic gates.

6. The controller of claim 1 wherein said delay line ADC comprises a delay cell array.

7. The controller of claim 1 wherein said delay line ADC is operative to provide a thermometer code output indicative of said difference between said compared voltages.

8. The controller of claim 7 wherein an extent of test signal propagation through said delay line ADC establishes said thermometer code.

9. The controller of claim 7 wherein said delay line ADC comprises an encoder operative to convert said thermometer code into said digital error signal.

16. The controller of claim 1 wherein said modulator is a digital pulse width modulator.

17. The controller of claim 1 wherein said modulator comprises a counter operative to determine a first component of a pulse-on period for said power control signal.

18. The controller of claim 1 wherein said modulator comprises a delay line operative to determine a second component of a pulse-on period for said power control signal.

19. The controller of claim 1 wherein said modulator comprises:

a counter operative to determine a first component of a pulse-on period for said power control signal; and

a delay line operative to determine a second component of said pulse-on period for said power control signal.

5. (canceled)

10-15. -15. (canceled)

20. An analog to digital converter (ADC) having an input voltage, said ADC comprising:

an array of delay cells, each powered by said input voltage; and

a signal tap array coupled to said delay cell array.

21. The ADC of claim 20 wherein said delay cells are digital logic gates.

22. The ADC of claim 20 wherein said ADC includes no passive analog components.

23. The ADC of claim 20 wherein a speed of test signal propagation through said delay cell array is substantially proportional to a magnitude of said input voltage.

24. The ADC of claim 23 wherein said signal tap array comprises a signal tap coupled to each said delay cell.

25. The ADC of claim 24 wherein statuses of said signal taps are indicative of said signal propagation speed through said delay cell array.

26. The ADC of claim 20 further comprising an encoder for converting thermometer code from said signal tap array into a digital error signal.

27. The ADC of claim 20 wherein said ADC includes no capacitors or inductors.

28. The ADC of claim 20 wherein said ADC includes no capacitors, inductors, or resistors.

29. A voltage controller, the controller comprising:

a voltage comparator operative to compare an analog voltage to an analog reference voltage and provide a digital error signal indicative of a difference between said output and reference voltages;

a compensator operative to determine a digital control signal based on said provided error signal; and

a modulator operative to provide a power control signal based on said determined digital control signal, wherein said comparator, said compensator, and said modulator are implemented entirely with digital logic gates.

30. The voltage controller of claim 29 wherein all of said digital logic gates correspond to standard library cells.

31. The voltage controller of claim 29 wherein all of said digital logic gates are HDL (hardware description language)-compatible.

32. The voltage controller of claim 29 wherein said controller includes no passive electronic components.

33. The voltage controller of claim 29 wherein said controller includes no analog energy storage components.

34. The voltage controller of claim 29 wherein said controller includes no capacitors, inductors, or resistors.

35. A method for controlling voltage, the method comprising:

comparing a converter output voltage with a reference voltage;

generating a digital error signal indicative of a result of said comparing; and

providing a power control signal indicative of said generated error signal, wherein said comparing, said generating, and said providing are performed entirely with digital logic gates.

36. The method of claim 35 wherein said comparing comprises powering a plurality of an array of delay cells with said converter output voltage.

37. The method of claim 35 wherein said comparing comprises measuring an extent of test signal propagation through an array of delay cells, said delay cells being powered by said converter output voltage.

38. The method of claim 35 wherein said providing comprises determining a digital control signal from said generated error signal according to a control algorithm.

39. The method of claim 38 wherein said determining comprises selecting a lookup table entry based on a value of said generated error signal.

40. The method of claim 35 wherein said providing comprises determining a duty ratio from said generated error signal according to a control algorithm.

41. A method of controlling voltage, the method comprising:

receiving a regulator output voltage;

converting said received output voltage into a digital error signal employing a delay line analog to digital converter (ADC); and

adjusting said regulator output voltage based on said digital error signal.

42. The method of claim 41 wherein said converting comprises:

powering a delay cell array with said received converter output voltage;

measuring a speed of test signal propagation through said powered delay cell array; and

generating said digital error signal indicative of said measured test signal propagation speed.

43. The method of claim 42 wherein said converting further comprises calibrating said delay line ADC.

44. The method of claim 43 wherein said calibrating comprises:

converting a reference voltage into a reference conversion error value employing said delay line ADC; and

adding said reference conversion error value to said digital error signal, thereby providing a corrected digital error signal.

45. The method of claim 43 wherein said calibrating comprises:

powering said delay cell array with a reference voltage;

measuring a speed of test signal propagation through said reference voltage-powered delay cell array;

generating a reference conversion error value indicative of said measured test signal propagation speed; and

adding said reference conversion error value to said generated digital error signal.

46. The method of claim 41 wherein said adjusting comprises determining a digital control signal based on said generated digital error signal according to a control algorithm.

47. A voltage controller comprising:

a source of converter output voltage;

an analog to digital converter (ADC) responsive to said output voltage to generate a digital error signal indicative of a difference between said output voltage and a previously stored reference voltage;

a digital electronic calculator responsive to said digital error signal to generate a digital control signal; and

a pulse width modulator responsive to said generated digital control signal to generate a pulse-on period for a power control signal;

wherein said ADC includes a delay line.

48. The voltage controller of claim 47 wherein said delay line ADC is responsive to a comparison between an active source of reference voltage and said previously stored reference voltage to generate a reference conversion error value.

49. The voltage controller of claim 48 wherein said delay line ADC comprises a register to store said reference conversion error value.

50. The voltage controller of claim 49 wherein said delay line ADC further comprises a voltage comparison circuit responsive to said digital error signal and said reference conversion error value to generate a sum of said digital error signal and said reference conversion error value.

51. (canceled)