Top layers of metal for integrated circuits

• US 20060063378A1
• Filed: 12/20/2004
• Published: 03/23/2006
• Est. Priority Date: 09/23/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megie Corporation
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming
• Granted Patent: US 7,381,642 B2
• Time in Patent Office: Days
• US Class Current: 438/642
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

Claims

1. A method for forming a post-passivation metallization system for integrated circuits, comprising:

providing an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting fine line metallization structure connected to said devices and comprising a plurality of first metal lines in one or more layers, and having a passivation layer formed thereover, with first openings in said passivation layer to contact pads connected to said first metal lines;

wherein said first openings are as small as 0.1 um; and

forming, in a selective deposition process, said post-passivation metallization system in said first openings and over said passivation layer, connected to said interconnecting fine line metallization structure, wherein said post-passivation metallization system comprises a plurality of top metal lines, in one or more layers, having a first sheet resistance smaller than a second sheet resistance of said first metal lines by at least 2 times.

2. The method of claim 1 wherein said post-passivation metallization system connects portions of said interconnecting fine line metallization structure to other portions of said interconnecting fine line metallization structure.

3. The method of claim 1 wherein said post-passivation metallization system connects portions of said interconnecting fine line metallization structure to external circuits by solder bumps, gold bumps, or wirebonds.

4. The method of claim 1 wherein said first sheet resistance of said post-passivation metallization system is smaller than 7 milliohms per square.

5. The method of claim 1, wherein said post-passivation metallization system comprises metal lines formed to a thickness of between about 2 and 1000 times thicker than metal lines in said interconnecting fine line metallization structure, and formed to a width of between about 2 and 1000 times the width of said first metal lines in said interconnecting fine line metallization structure.

6. The method of claim 1 wherein said first sheet resistance is smaller than said second sheet resistance by at least 5 times.

7. The method of claim 1 wherein said first sheet resistance is smaller than said second sheet resistance by at least 10 times.

8. A method for forming a post-passivation metallization system for high performance integrated circuits, comprising:

providing an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting fine line metallization structure connected to said devices and comprising a plurality of first metal lines in one or more layers, and having a passivation layer formed thereover, with first openings in said passivation layer to contact pads connected to said first metal lines;

depositing a polymer layer over said passivation layer, and forming second openings in said polymer layer to expose said contact pads, wherein said second openings in said polymer layer are lined up with said first openings in said passivation layer; and

forming, in a selective deposition process, said post-passivation metallization system in said first openings, said second openings, and over said polymer layer, connected to said interconnecting fine line metallization structure, wherein said post-passivation metallization system comprises a plurality of top metal lines, in one or more layers, having a first sheet resistance smaller than 7 milliohms per square.

9. The method of claim 8 wherein said post-passivation metallization system connects portions of said interconnecting fine line metallization structure to other portions of said interconnecting fine line metallization structure.

10. The method of claim 8 wherein said post-passivation metallization system connects portions of said interconnecting fine line metallization structure to external circuits by solder bumps, gold bumps, or wirebonds.

11. The method of claim 8 wherein said first sheet resistance is smaller than a second sheet resistance of said first metal lines by at least 2 times.

12. The method of claim 8 wherein said first sheet resistance is smaller than a second sheet resistance of said first metal lines by at least 5 times.

13. The method of claim 8 wherein said first sheet resistance is smaller than a second sheet resistance of said first metal lines by at least 10 times.

14. A semiconductor device structure, comprising:

semiconductor devices formed on a semiconductor substrate, with an overlaying interconnecting fine line metallization structure connected to said devices and comprising a plurality of first metal lines in one or more layers, and having a passivation layer formed thereover, with first openings in said passivation layer to contact pads connected to said first metal lines, wherein said first openings are as small as 0.1 um; and

a post-passivation metallization system formed in said openings and over said passivation layer, connected to said interconnecting metallization structure, wherein said post-passivation metallization system comprises a plurality of top metal lines, in one or more layers, having a first sheet resistance smaller than a second sheet resistance of said first metal lines by at least 2 times.

15. The structure of claim 14 wherein said semiconductor devices comprise n-channel MOS devices, p-channel MOS devices, and/or CMOS devices.

16. The structure of claim 14 wherein each of said top metal lines comprises copper (Cu), gold (Au), silver (Ag), palladium (Pd), or nickel (Ni) and has a thickness of between about 2 and 100 microns.

17. The structure of claim 14 wherein said first sheet resistance is smaller than 7 milliohms per square.

18. The structure of claim 14 wherein said first sheet resistance is smaller than said second sheet resistance by at least 5 times.

19. The structure of claim 14 wherein said first sheet resistance is smaller than said second sheet resistance by at least 10 times.

20. A semiconductor device structure, comprising:

an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting fine line metallization structure connected to said devices and comprising a plurality of first metal lines in one or more layers, and having a passivation layer formed thereover, with first openings in said passivation layer to contact pads connected to said first metal lines;

a polymer layer over said passivation layer, and second openings in said polymer layer to expose said contact pads, wherein said second openings in said polymer layer are lined up with said first openings in said passivation layer; and

a post-passivation metallization system in said first and second openings and over said polymer layer, connected to said interconnecting fine line metallization structure, wherein said post-passivation metallization system comprises a plurality of top metal lines, in one or more layers, having a first sheet resistance smaller than 7 milliohms per square.

21. The structure of claim 20 wherein said semiconductor devices comprise n-channel MOS devices, p-channel MOS devices, and/or CMOS devices.

22. The structure of claim 20 wherein each of said top metal lines comprises copper (Cu), gold (Au), silver (Ag), palladium (Pd), or nickel (Ni) and has a thickness of between about 2 and 100 microns.

23. The structure of claim 20 wherein said first sheet resistance is smaller than a second sheet resistance of said first metal lines by at least 2 times.

24. The structure of claim 20 wherein said first sheet resistance is smaller than a second sheet resistance of said first metal lines by at least 5 times.

25. The structure of claim 20 wherein said first sheet resistance is smaller than a second sheet resistance of said first metal lines by at least 10 times.