Semiconductor device with double barrier film

• US 20060065913A1
• Filed: 12/02/2004
• Published: 03/30/2006
• Est. Priority Date: 09/28/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sugimae, Kikuko, Arai, Fumitaka, Matsunaga, Yasuhiko, Sakuma, Makoto
• Granted Patent: US 7,078,813 B2
• Time in Patent Office: Days
• US Class Current: 257/202
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

Claims

1. A semiconductor device comprising:

a gate insulated field-effect transistor having a gate electrode that is provided via a gate insulation film on a semiconductor substrate, a metal layer that is provided on the gate electrode, and diffusion layers that are separately provided in the semiconductor substrate such that the gate electrode is provided on a region lying between the diffusion layers, each of the diffusion layers serving as a source or a drain;

a first barrier film that is provided on the diffusion layers and on side walls of the transistor;

a first insulation layer that is provided on the first barrier film;

a second barrier film that is continuously provided on the metal layer and on the first insulation layer;

a trench that is opened in the second barrier film with a first width and extends in a first direction;

a second insulation layer that is provided on the second barrier film;

an upper contact hole portion that penetrates the second insulation layer and has a bottom in the second barrier film, the bottom having a second width greater than the first width in a second direction crossing the first direction;

a lower contact hole portion that penetrates the first insulation layer and the first barrier film from the upper contact hole portion through the trench and is provided on the diffusion layer, an upper portion of the lower contact hole portion having the first width in the second direction; and

a contact plug provided in the upper contact hole portion and the lower contact hole portion.

2. The device according to claim 1, wherein the second barrier film has a greater thickness than the first barrier film.

3. The device according to claim 1, wherein the first and second barrier films function as barriers against reactions between the first insulation layer and the metal layer and between the second insulation layer and the metal layer.

4. The device according to claim 1, wherein the first and second barrier films function as stoppers at a time of forming the upper contact hole portion and the lower contact hole portion.

5. The device according to claim 1, further comprising:

a memory cell row that is arranged in the first direction and includes a plurality of series-connected memory cell transistors having sources and drains shared; and

select transistors that are arranged at both ends of the memory cell row and select the memory cell row.

6. The device according to claim 5, wherein the insulated gate field-effect transistor is the select transistor.

7. The device according to claim 5, wherein each of the plurality of memory cell transistors comprises:

a floating electrode provided via the gate insulation film on the substrate;

an inter-gate insulation film provided on the floating electrode;

a control electrode provided on the inter-gate insulation film; and

a silicide layer provided on the control electrode.

8. The device according to claim 5, wherein the memory cell row and the select transistors are provided in a memory cell array.

9. A semiconductor device comprising:

a memory cell row that is arranged in a first direction and includes a plurality of series-connected memory cell transistors having sources and drains shared, each of the plurality of memory cell transistors including,

a floating electrode provided via a gate insulation film on a semiconductor substrate,

an inter-gate insulation film provided on the floating electrode, and

a control electrode provided on the inter-gate insulation film;

select transistors that are arranged at both ends of the memory cell row and select the memory cell row, each of the select transistors including a gate electrode provided via the gate insulation film on the substrate;

a metal layer that is provided on the control electrode and on the gate electrode;

a first barrier film that is provided on diffusion layers, which are located between two said select transistors of different said memory cell rows that are adjacent in the first direction, and on opposed side surfaces of the two select transistors;

a first insulation layer that is provided on the first barrier film;

a second barrier film that is continuously provided on the metal layer and on the first insulation layer;

a trench that is disposed between the two select transistors, includes an opening portion with a first width in the second barrier film, and extends in a second direction crossing the first direction;

a second insulation layer that is provided on the second barrier film;

an upper contact hole portion that penetrates the second insulation layer and has a bottom in the second barrier film, the bottom having a second width greater than the first width in the first direction;

a lower contact hole portion that penetrates the first insulation layer and the first barrier film from the upper contact hole portion through the trench and is provided on the diffusion layer; and

a contact plug provided in the upper contact hole portion and the lower contact hole portion.

10. The device according to claim 9, wherein the second barrier film has a greater thickness than the first barrier film.

11. The device according to claim 9, wherein the first and second barrier films function as barriers against reactions between the first insulation layer and the metal layer and between the second insulation layer and the metal layer.

12. The device according to claim 9, wherein the first and second barrier films function as stoppers at a time of forming the upper contact hole portion and the lower contact hole portion.

13. The device according to claim 9, wherein the memory cell row and the select transistors are provided in a memory cell array.

14. A semiconductor device comprising:

a transistor having a gate electrode that is provided via a gate insulation film on a semiconductor substrate, a metal layer that is provided on the gate electrode, and diffusion layers that are separately provided in the semiconductor substrate such that the gate electrode is provided on a region lying between the diffusion layers, each of the diffusion layers serving as a source or a drain;

a first barrier film that is provided on the diffusion layer, which serves as the source or drain of the transistor, and on side walls of the transistor;

a first insulation layer that is provided on the first barrier film;

a second barrier film that is continuously provided on the metal layer and on the first insulation layer;

a second insulation layer that is provided on the second barrier film;

an opening portion that is provided in the second barrier film and is located over the diffusion layer;

a first contact plug that continuously penetrates the second insulation layer, the first insulation layer and the first barrier layer through the opening portion, and is provided on the diffusion layer; and

a second contact plug that continuously penetrates the second insulation layer, the second barrier film and the metal layer and establishes electrical connection to the gate electrode.

15. The device according to claim 14, wherein the second barrier film has a greater thickness than the first barrier film.

16. The device according to claim 14, wherein the first and second barrier films function as barriers against reactions between the first insulation layer and the metal layer and between the second insulation layer and the metal layer.

17. The device according to claim 14, wherein the first and second barrier films function as stoppers at a time of forming the first contact plug and the second contact plug.

18. The device according to claim 14, further comprising a memory cell array that comprises:

a memory cell row; and

a select transistor that selects the memory cell row,

wherein the transistor is a peripheral transistor that is provided in a peripheral circuit formed near the memory cell array.

19. The device according to claim 18, wherein the memory cell row is arranged in a first direction and includes a plurality of series-connected memory cell transistors having sources and drains shared, each of the plurality of memory cell transistors comprising:

a floating electrode provided via the gate insulation film on the semiconductor substrate;

an inter-gate insulation film provided on the floating electrode;

a control electrode provided on the inter-gate insulation film,

wherein the peripheral transistor transfers a write voltage to the control electrode.