Method and system for writing data to MEMS display elements

• US 20060066561A1
• Filed: 09/22/2005
• Published: 03/30/2006
• Est. Priority Date: 09/27/2004
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Chui, Clarence, Kothari, Manish
• Granted Patent: US 8,310,441 B2
• Time in Patent Office: Days
• US Class Current: 345/108
• CPC Class Codes: G09G 2300/06 Passive matrix structure, i.e. with direct application of both column and row voltages to the light emitting or modulating elements, other than LCD or OLED
• CPC Class Codes: G09G 2310/0245 Clearing or presetting the whole screen independently of waveforms, e.g. on power-on G09G2310/063 takes precedence
• CPC Class Codes: G09G 2310/0254 Control of polarity reversal in general, other than for liquid crystal displays
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 3/3466 based on interferometric effect

Abstract

Charge balanced display data writing methods use write and hold cycles of opposite polarity during selected frame update periods. A release cycle may be provided to reduce the chance that a given display element wil become stuck in an actuated state.

Claims

1. A method of actuating a MEMS display element, said MEMS display element comprising a portion of an array of MEMS display elements, said method comprising:

writing display data to said MEMS display element with a potential difference of a first polarity during a first portion of a display write process;

re-writing said display data to said MEMS display element with a potential difference having a polarity opposite said first polarity during a second portion of said display write process.

applying a first bias potential having said first polarity to said MEMS display element during a third portion of said display write process; and

applying a second bias potential having said opposite polarity to said MEMS display element during a fourth portion of said display write process.

2. The method of claim 1, wherein said first portion of said display write process comprises writing a first frame of display data to said array of MEMS display elements, and wherein said second portion of said display write process comprises re-writing said first frame of display data to said array of MEMS display elements.

3. The method of claim 2, wherein said third and fourth portions of said display write process comprises holding said first frame of display data following said re-writing.

4. The method of claim 3, additionally comprising writing a second frame of display data using said writing, re-writing, applying a first bias potential and applying a second bias potential.

5. The method of claim 1, wherein said first portion of said display write process comprises writing a first row of display data to said array of MEMS display elements, and wherein said second portion of said display write process comprises re-writing said first row of display data to said array of MEMS display elements.

6. The method of claim 5, wherein said third and fourth portions of said display write process comprises holding said first row of display data following said re-writing.

7. The method of claim 6, additionally comprising writing a second row of display data using said writing, re-writing, applying a first bias potential and applying a second bias potential.

8. The method of claim 1, wherein said first, second, third, and fourth portions of said display write process each comprise approximately one-fourth of a time period defined by the inverse of a rate at which frames of display data are received by a display system.

9. The method of claim 1, wherein said first portion and said second portion together comprise less than ½

of a time period defined by the inverse of a rate at which frames of display data are received by a display system.

10. The method of claim 1, wherein said first portion extends for a first time periods and said second portion extends for a second time period.

11. The method of claim 10, wherein said first and second time periods are different.

12. The method of claim 11, wherein said first and second time periods are determined based at least in part on a polarity dependent dielectric charging rate.

13. A method of maintaining a frame of display data on an array of MEMS display elements, said method comprising alternately applying approximately equal bias voltages of opposite polarities to said MEMS display elements for periods of time defined at least in part by the inverse of a rate at which frames of display data are received by a display system.

14. The method of claim 13, wherein each said period of time is substantially equal to 1/(2 f), wherein f is a defined frequency of frame refresh cycles.

15. The method of claim 13, wherein each said period of time is substantially equal to 1/(4 f), wherein f is a defined frequency of frame refresh cycles.

16. A method writing frames of display data to an array of MEMS display elements at a rate of one frame per defined frame update period, said method comprising:

writing display data to said MEMS display elements, wherein said writing takes less than said frame update period; and

applying a series of bias potentials of alternating polarity to said MEMS display elements for the remainder of said frame update period.

17. The method of claim 16 wherein said series comprises an application of a first polarity during approximately half of said remainder of said frame update period, and an application of a second opposite polarity during approximately half of said frame update period.

18. A MEMS display device configured to display images at a frame update rate, said frame update rate defining a frame update period, said display device comprising a column driver circuit configured to apply a polarity balanced sequence of bias voltages to substantially all columns of a MEMS display array for portions of at least one frame update period, wherein said portions are defined by a time remaining between completing a frame write process for a first frame, and beginning a frame write process for a next subsequent frame.

19. The MEMS display device of claim 18, wherein said driver circuit is configured to apply the same voltage to substantially all columns of said display array during a portion of said frame update period.

20. A method of driving a MEMS display comprising periodically releasing substantially all pixels of said display, wherein said periodic releasing occurs for each pixel at an infrequent rate such that there is no perceptible affect on visual appearance of the display to a normal observer.

21. The method of claim 20, wherein any given periodically released pixel is released at a rate slower than once per hour of display use.

22. The method of claim 20, wherein any given periodically released pixel is released at a rate slower than once per 100,000 displayed frames of image data.