Integrated circuit memory system having dynamic memory bank count and page size

• US 20060067146A1
• Filed: 09/30/2004
• Published: 03/30/2006
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Bellows, Chad A., Richardson, Wayne S., Kim, Jun, Ching, Michael, Woo, Steven, Knorpp, Kurt T.
• Granted Patent: US 7,254,075 B2
• Time in Patent Office: Days
• US Class Current: 365/206
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.

Claims

1. An integrated circuit memory device, comprising:

a storage array having a first and second row of storage cells; and

a row of sense amplifiers including a first plurality of sense amplifiers and a second plurality of sense amplifiers, coupled to the storage array, to access the first and second rows of storage cells, wherein the integrated circuit memory device is operable in a first mode and second mode of operation, wherein;

during the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers, and

during the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers.

2. The integrated circuit memory device of claim 1, wherein the second and third plurality of data is accessible simultaneously from an interface coupled to the row of sense amplifiers during the second mode of operation.

3. The integrated circuit memory device of claim 1, wherein the second plurality of data is transferred from a first half of the first row and the third plurality of data is transferred from a second half of the second row during the second mode of operation.

4. The integrated circuit memory device of claim 3, wherein the first half of the first row is activated and the second half of the second row is activated during the second mode of operation.

5. The integrated circuit memory device of claim 3, wherein the first plurality of sense amplifiers is precharged and the second plurality of sense amplifiers is precharged during the second mode of operation.

6. The integrated circuit memory device of claim 3, wherein the first plurality of sense amplifiers is activated and the second plurality of sense amplifiers is precharged during the second mode of operation.

7. The integrated circuit memory device of claim 1, wherein the storage array is included in a first memory bank in a plurality of memory banks in the integrated circuit memory device.

8. The integrated circuit memory device of claim 1, wherein during the first mode of operation the integrated circuit has a first bank count and first page size and during the second mode of operation the integrated circuit has a second bank count and second page size.

9. The integrated circuit memory device of claim 8, wherein the second bank count is greater than the first bank count and the first page size is larger than the second page size.

10. A memory system comprising:

a master device; and

an integrated circuit memory device, including;

a storage array having a first and second row of storage cells; and

a row of sense amplifiers including a first plurality of sense amplifiers and a second plurality of sense amplifiers, coupled to the storage array, to access the first and second rows of storage cells, wherein the integrated circuit memory device is operable in a first mode and second mode of operation, wherein;

during the first mode of operation, a first plurality of data is transferred from the first row of storage cells to the row of sense amplifiers, and

during the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers.

11. The memory system of claim 10, wherein the integrated circuit memory device includes an interface coupled to the plurality of sense amplifiers and the master device, wherein the second and third plurality of data is accessible simultaneously from the interface coupled to the row of sense amplifiers during the second mode of operation.

12. The memory system of claim 10, wherein the second plurality of data is transferred from a first half of the first row and the third plurality of data is transferred from a second half of the second row during the second mode of operation.

13. The memory system of claim 12, wherein the first half of the first row is activated in response to a first activation command generated by the master device and the second half of the second row is activated in response to a second activation command generated by the master device during the second mode of operation.

14. The memory system of claim 12, wherein the first plurality of sense amplifiers is precharged in response to a first precharge command generated by the master device and the second plurality of sense amplifiers is precharged in response to a second precharge command generated by the master device during the second mode of operation.

15. The memory system of claim 10, wherein the master device generates a control signal to the integrated circuit memory device to determine whether the integrated circuit memory device operates in either the first or second mode of operation.

16. The integrated circuit memory device of claim 10, wherein during the first mode of operation the integrated circuit has a first bank count and first page size and during the second mode of operation the integrated circuit has a second bank count and second page size.

17. The integrated circuit memory device of claim 16, wherein the second bank count is greater than the first bank count and the first page size is larger than the second page size.

18. The memory system of claim 10, wherein the master device generates the control signal in response to power consumption value.

19. The memory system of claim 10, wherein the master device generates the control signal in response to executable machine-readable instructions.

20. The memory system of claim 19, wherein the executable machine-readable instructions are included in application software.

21. The memory system of claim 19, wherein the executable machine-readable instructions are included in operating system software.

22. The memory system of claim 10, wherein the master device is a graphics controller.

23. The memory system of claim 10, wherein the master device is a memory controller.

24. The memory system of claim 10, wherein the master device is a network controller.

25. A method for operation of an integrated circuit memory device, comprising:

transferring a first plurality of data from a first row of storage cells in a first memory bank to a first plurality of sense amplifiers in a plurality of sense amplifiers; and

transferring a second plurality data from a second row of storage cells in the first memory bank to a second plurality of sense amplifiers in the plurality of sense amplifiers.

26. The method of claim 25, further comprising:

transferring the first and second plurality of data from the plurality of sense amplifiers to an interface.

27. The method of claim 25, wherein the first memory bank, coupled to the plurality of sense amplifiers, is included in a plurality of memory banks.

28. The method of claim 25, further comprising:

activating a first subset of the first row; and

activating a second subset of the second row.

29. The method of claim 28, wherein the first subset is a first half and the second subset is a second half.

30. The method of claim 28, further comprising:

precharging the first plurality of sense amplifiers.

31. The method of claim 28, further comprising:

precharging the first plurality of sense amplifiers; and

precharging the second plurality of sense amplifiers.

32. The method of claim 31, wherein the first plurality is a first half of the plurality of sense amplifiers;

and the second plurality is the second half of the plurality of sense amplifiers.

33. The method of claim 25, further comprising:

adjusting a number of memory banks in the integrated circuit memory device; and

,

adjusting a page size of the integrated circuit memory device.

34. An integrated circuit memory device, comprising:

a memory bank having a first and second row of storage cells to store a first and second plurality of data in respective subsets of the first and second rows, respectively; and

means for transferring the first and second plurality of data to a plurality of sense amplifiers, wherein the first and second plurality of data is stored in the plurality of sense amplifiers concurrently.

35. The integrated circuit memory device of claim 34, wherein the integrated circuit memory device includes a plurality of memory banks and the memory bank is a first memory bank of the plurality of memory banks.