Power led package

• US 20060071329A1
• Filed: 09/24/2004
• Published: 04/06/2006
• Est. Priority Date: 09/24/2004
• Status: Active Grant

• Current Assignee: Gelcore (General Electric Company)
• Original Assignee: Gelcore (General Electric Company)
• Inventors: Du, Shawn X.
• Granted Patent: US 7,081,667 B2
• Time in Patent Office: Days
• US Class Current: 257/723
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a chip package (10, 10′, 110, 210), first and second electrical power buses (14, 14′, 16, 16′, 114, 116, 214, 216) are each formed of an electrical conductor having a chip bonding portion (20, 22, 120, 122, 220, 222) and a lead portion (26, 26′, 28, 28′, 126, 128, 226, 228) extending away from the chip bonding portion. The chip bonding portions of the first and second electrical power buses have edges (32, 34, 132, 134, 232, 234) spaced apart from one another to define an extended electrical isolation gap (40, 140, 240). A plurality of chips (42, 44, 46, 142, 143, 144, 145, 146, 147, 148, 242) straddle the extended electrical isolation gap and are electrically connected with the first and second electrical power buses to receive electrical power from the first and second electrical power buses.

Claims

1. A chip package comprising:

an electrically insulating substrate having a front principal side;

planar first and second electrical power buses each having a chip bonding portion and a lead portion extending away from the chip bonding portion, at least the chip bonding portions of the first and second electrical power buses being disposed on the front principal side of the substrate and having edges spaced apart from one another to define an extended electrical isolation gap; and

a plurality of chips straddling the extended electrical isolation gap and electrically connected with the first and second electrical power buses to receive electrical power from the first and second electrical power buses.

2. The chip package as set forth in claim 1, wherein the lead portions of the planar first and second electrical power buses extend off the front principal side of the substrate.

3. The chip package as set forth in claim 2, wherein the lead portions of the planar first and second electrical power buses wrap around to a back principal side of the substrate opposite the front principal side.

4. The chip package as set forth in claim 1, wherein the chips include light emitting chips, the chip package further comprising:

a light transmissive encapsulant disposed on the substrate and encapsulating the plurality of chips and the chip bonding portions of the planar first and second electrical power buses.

5. The chip package as set forth in claim 1, wherein the planar first electrical power bus is a rectangular strip, the planar second electrical power bus is a rectangular strip, and ends of the planar first and second electrical power buses are arranged offset in parallel with one another to define the extended electrical isolation gap.

6. The chip package as set forth in claim 1, wherein the planar first and second electrical power buses are interchangeable.

7. The chip package as set forth in claim 1, wherein (i) the chip bonding portion of the first power bus includes a broadened end and (ii) the chip bonding portion of the second power bus includes a broadened end that wraps around the broadened end of the chip bonding portion of the first power bus to define the extended electrical isolation gap.

8. The chip package as set forth in claim 1, wherein the chip bonding portions of the first and second power buses include interdigitated fingers that define the extended electrical isolation gap.

9. The chip package as set forth in claim 1, wherein the lead portions of the planar first and second electrical power buses extend away from a chip bonding region defined by the chip bonding portions of the first and second electrical power buses in generally opposite directions.

10. A chip package comprising:

first and second electrical power buses each formed of an electrical conductor having a chip bonding portion and a lead portion extending away from the chip bonding portion, the chip bonding portions of the first and second electrical power buses having edges spaced apart from one another to define an extended electrical isolation gap; and

a plurality of chips straddling the extended electrical isolation gap and electrically connected with the first and second electrical power buses to receive electrical power from the first and second electrical power buses.

11. The chip package as set forth in claim 10, further comprising:

an electrically insulating substrate, at least the chip bonding portions of the first and second electrical power buses being secured to a front side of the substrate.

12. The chip package as set forth in claim 11, wherein the electrically insulating substrate is also thermally insulating, heat generated by the plurality of chips being conducted from the chip bonding portions of the first and second power buses to distal ends of the lead portions of the first and second power buses.

13. The chip package as set forth in claim 11, wherein the lead portions of the first and second power buses extend off of the electrically insulating substrate.

14. The chip package as set forth in claim 13, wherein the lead portions of the first and second power buses wrap around to a back side of the electrically insulating substrate opposite the front side to define back side surface mount bonding pads.

15. The chip package as set forth in claim 10, wherein the electrical conductor forming the first electrical power bus is sheet metal, and the electrical conductor forming the second electrical power bus is sheet metal.

16. The chip package as set forth in claim 15, wherein the first and second electrical power buses are linear conductive strips arranged parallel to one another and relatively offset from one another to define neighboring and non-neighboring portions of each strip, the neighboring portions being the chip bonding portions and the non-neighboring portions being the lead portions.

17. The chip package as set forth in claim 10, further comprising:

an electrostatic discharge protection device straddling the extended electrical isolation gap and electrically connected across the first and second electrical power buses, the electrostatic discharge protection device providing electrostatic discharge protection for the plurality of chips.

18. The chip package as set forth in claim 10, further comprising:

a filter circuit straddling the extended electrical isolation gap and electrically connected across the first and second electrical power buses, the filter circuit providing one of low pass, high pass, and bandpass filtering for electrical power delivered by the first and second electrical power buses.

19. The chip package as set forth in claim 10, further comprising:

a filtering capacitor straddling the extended electrical isolation gap and electrically connected across the first and second electrical power buses, the filtering capacitor suppressing high frequency components of electrical power delivered by the first and second electrical power buses.

20. The chip package as set forth in claim 10, wherein the chips include light emitting diode chips, the chip package further comprising:

a light-transmissive encapsulant surrounding the light emitting diode chips and the chip bonding portions of the first and second electrical power buses.

21. A chip operating method comprising:

forming first and second electrical power buses each having a chip bonding portion and a lead portion extending away from the chip bonding portion;

disposing at least the chip bonding portions of the formed first and second electrical power buses on a front principal side of an electrically insulating substrate with edges of the chip bonding portions arranged spaced apart from one another to define an extended electrical isolation gap; and

bonding a plurality of chips across the extended electrical isolation gap and electrically connected with the first and second electrical power buses to receive electrical operating power via the first and second electrical power buses.

22. The chip operating method as set forth in claim 21, wherein the forming of the first and second electrical power buses comprises:

cutting sheet metal to form the first and second electrical power buses.

23. The chip operating method as set forth in claim 21, wherein the disposing of at least the chip bonding portions of the formed first and second electrical power buses on the front principal side of the substrate leaves at least part of each lead portion extending off the front principal side, the method further comprising:

wrapping the part of each lead portion extending off the front principal side around the substrate to define back side surface mount bonding pads.

24. The chip operating method as set forth in claim 21, wherein the chips include light emitting diode chips, and the bonding of the plurality of chips across the extended electrical isolation gap comprises:

flip-chip bonding the light emitting diode chips to the first and second electrical power buses.