Semiconductor device and method of manufacturing semiconductor device

• US 20060076622A1
• Filed: 09/30/2005
• Published: 04/13/2006
• Est. Priority Date: 10/07/2004
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Saito, Masaki, Wang, Junli, Kataoka, Toyotaka
• Granted Patent: US 7,538,390 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A semiconductor device including an NMOS region and a PMOS region in the same substrate, wherein the semiconductor device includes a strained Si layer which is provided on the substrate in the NMOS region and in which the surface has a plane orientation different from that of the substrate, and a strained SiGe layer which is provided on the substrate in the PMOS region and which is composed of a stained layer having the same plane orientation as that of the surface of the substrate; and a method of manufacturing the same.

Claims

1. A semiconductor device comprising a first device region and a second device region in the same substrate, wherein said semiconductor device comprises:

a first semiconductor layer provided on said substrate in said first device region and having a plane orientation different from that of the surface of said substrate; and

a second semiconductor layer provided on said substrate in said second semiconductor region and comprised of a strained layer having the same plane orientation with that of the surface of said substrate.

2. The semiconductor device as set forth in claim 1, wherein

said first device region is an NMOS transistor region, while said second device region is a PMOS transistor region;

and

the plane orientation of said first semiconductor layer is (100), and said second semiconductor layer is comprised of a strained layer in a compression-strained state.

3. The semiconductor device as set forth in claim 1, wherein

said first device region is a PMOS transistor region, while said second device region is an NMOS transistor region;

and

the plane orientation of said first semiconductor layer is (110), and said second semiconductor layer is comprised of a strained layer in a tension-strained state.

4. The semiconductor device as set forth in claim 1, wherein

said first semiconductor layer is formed of a strained layer.

5. The semiconductor device as set forth in claim 4, wherein

said first device region is an NMOS transistor region, while said second device region is a PMOS transistor region;

said first semiconductor layer is comprised of a strained layer in a tension-strained state with a plane orientation of (100); and

said second semiconductor layer is comprised of a strained layer in a compression-strained state with a plane orientation of (110).

6. The semiconductor device as set forth in claim 4, wherein

said first device region is a PMOS transistor region, while said second device region is an NMOS transistor region;

said first semiconductor layer is comprised of a strained layer in a compression-strained state with a plane orientation of (110); and

said second semiconductor layer is comprised of a strained layer in a tension-strained state with a plane orientation of (100).

7. The semiconductor device as set forth in claim 1, wherein

said first semiconductor layer is laminated on said substrate through an insulation layer therebetween;

and

said second semiconductor layer is formed on said substrate by epitaxial growth.

8. A method of manufacturing a semiconductor device comprising a first device region and a second device region in the same substrate, said method comprising the steps of:

laminating, with an insulation layer formed on said substrate, a first semiconductor layer having a plane orientation different from the surface of said substrate, on said insulation layer;

exposing said substrate by removing said insulation layer and said first semiconductor layer, in said second device region; and

epitaxially growing a second semiconductor layer comprised of a strained layer on said exposed substrate in said second device region in the condition of maintaining the plane orientation of the surface of said substrate.

9. A method of manufacturing a semiconductor device as set forth in claim 8, wherein

said first device region is an NMOS transistor region, while said second device region is a PMOS transistor region;

said first semiconductor layer with a plane orientation of (100) is laminated on said insulation layer in said laminating step; and

said second semiconductor layer comprised of said strained layer in a compression-strained state is epitaxially grown in said epitaxially growing step.

10. A method of manufacturing a semiconductor device as set forth in claim 8, wherein

said first device region is a PMOS transistor region, while said second device region is an NMOS transistor region;

said first semiconductor layer with a plane orientation of (110) is laminated on said insulation layer in said laminating step; and

said second semiconductor layer comprised of said strained layer in a tension-strained state is epitaxially grown in said epitaxially growing step.

11. A method of manufacturing a semiconductor device as set forth in claim 8, wherein

said first semiconductor layer is formed of a strained layer.

12. A method of manufacturing a semiconductor device as set forth in claim 11, wherein

said first device region is an NMOS transistor region, while said second device region is a PMOS transistor region;

said first semiconductor layer comprised of the strained layer in a tension-strained state with a plane orientation of (100) is laminated on said insulation layer in said laminating step; and

said second semiconductor layer comprised of the strained layer in a compression-strained state with a plane orientation of (110) is epitaxially grown in said epitaxially growing step.

13. A method of manufacturing a semiconductor device as set forth in claim 11, wherein

said first device region is a PMOS transistor region, while said second device region is an NMOS transistor region;

said first semiconductor layer comprised of the strained layer in a compression-strained state with a plane orientation of (110) is laminated on said insulation layer in said laminating step; and

said second semiconductor layer comprised of the strained layer in a tension-strained state with a plane orientation of (100) is epitaxially grown in said epitaxially growing step.