Low power clocking systems and methods

• US 20060080566A1
• Filed: 09/29/2005
• Published: 04/13/2006
• Est. Priority Date: 03/21/2001
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: Gallitzin Allegheny LLC (Intellectual Ventures LLC)
• Inventors: Sherburne, Robert Warren Jr.
• Granted Patent: US 7,398,414 B2
• Time in Patent Office: Days
• US Class Current: 713/500
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: H04W 52/0293 having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of each processing unit to optimize speed and processing power for a task; and a high-density memory array core coupled to the processing units.

Claims

1-20. -20. (canceled)

21. An integrated circuit comprising:

a first processor unit of the integrated circuit capable of receiving a first clock to control the first processor unit;

a first buffer capable of receiving data from an output of the first processor unit, the first buffer configured to provide a feedback signal to a first clock controller;

a second processor unit of the integrated circuit capable of receiving the data from the first buffer and configured to receive a second clock to control the second processor unit; and

the first clock controller capable of controlling the first clock based on the feedback signal.

22. The integrated circuit of claim 21, further comprising a memory of the integrated circuit coupled to the first processor unit and the second processor unit.

23. The integrated circuit of claim 21, further comprising a wireless transceiver coupled to the first processor unit and the second processor unit.

24. The integrated circuit of claim 21, further comprising a reconfigurable processor core including the first processor unit and the second processor unit.

25. The integrated circuit of claim 21, wherein the first clock controller is configured to vary the first clock based on the feedback signal.

26. The integrated circuit of claim 21, further comprising a second clock controller configured to control the second clock.

27. The integrated circuit of claim 21, wherein the first clock controller is configured to provide a write signal to the first buffer and is configured to provide a read signal to an input buffer coupled to an input of the first processor unit.

28. The integrated circuit of claim 21, wherein the first clock controller is configured to lower the first clock by a first amount if the feedback signal is greater than a first threshold.

29. The integrated circuit of claim 28, wherein the first clock controller is configured to lower the first clock by a second amount if the feedback signal is greater than a second threshold, wherein the second amount and the second threshold are greater than the first amount and the first threshold, respectively.

30. A system comprising:

an integrated circuit including a digital portion and an analog portion, the digital portion having;

a reconfigurable processor core including;

a first processor capable of receiving a first clock to control the first processor;

a first buffer capable of receiving data from an output of the first processor, the first buffer configured to provide a feedback signal to a first clock controller;

a second processor capable of receiving the data from the first buffer and configured to receive a second clock to control the second processor; and

the first clock controller capable of controlling the first clock based on the feedback signal; and

the analog portion having radio frequency (RF) circuitry capable of communicating baseband data from the reconfigurable processor core.

31. The system of claim 30, further comprising a second buffer coupled to an input of the first processor, the second buffer capable of being controlled by the first clock.

32. The system of claim 30, wherein the first clock controller is configured to provide a write signal to the first buffer based on the feedback signal, wherein the write signal corresponds to the first clock.

33. The system of claim 30, wherein the first clock controller is configured to lower a frequency of the first clock if the feedback signal is above a threshold.

34. The system of claim 33, wherein the threshold is adjustable.

35. A method comprising:

clocking a first processor of an integrated circuit with a first clock;

clocking a second processor of the integrated circuit with a second clock, the second clock different than the first clock;

clocking a buffer coupled to provide data from the first processor to the second processor with the first clock; and

using at least one clock controller to generate a frequency of the first clock and the second clock from a third clock to control the first processor and the second processor.

36. The method of claim 35, further comprising generating a fourth clock from the third clock to control a wireless transceiver on the integrated circuit using the at least one clock controller.

37. The method of claim 35, further comprising maintaining the third clock at a fixed frequency.

38. The method of claim 35, further comprising varying the first clock based on a feedback signal from the buffer.

39. The method of claim 38, further comprising varying the second clock based on a feed forward signal from the buffer.

40. The method of claim 38, further comprising generating the feedback signal based on a comparison between a level of the buffer and a threshold.