ASICs having more features than generally usable at one time and methods of use

• US 20060080631A1
• Filed: 10/12/2004
• Published: 04/13/2006
• Est. Priority Date: 10/12/2004
• Status: Active Grant

• Current Assignee: Sheyu Group LLC (Intellectual Ventures LLC)
• Original Assignee: Nanotec Corporation
• Inventors: Koo, James T.
• Granted Patent: US 7,251,805 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different market spaces (e.g., in different countries where different interoperability standards are chosen) and a subset of the excessive ASIC functionality is programmably activated in each market space after manufacture. Customer behavior can be fickle. If market trends evolve towards demand for functionality #2 instead of an originally, more expected, functionality #1, the mass produced of the crammed chip (or chip set) is not out of necessarily out of luck. If the mass produced had enough foresight to cram in functionality #2 as well as functionality #1, the producer can programmably activate #2, and deactivate #1 as market demand suddenly shifts in a given market space. In one embodiment, a mega-ASIC with excessive ASIC functionality crammed into it, has a universal core as well as plurality of programmably selectable ASIC function blocks. The ASIC function blocks are programmably activatable and de-activatable so that a mass produced can quickly respond to shifting market demands, thus addresses both time to market and product life issues. The invention allows a small chip designer to simultaneously address more than one market or customer space with one ASIC chip thereby reducing the design cost per product design. By selectively activating the excessive and selectable ASIC functionalities, the small ASIC chip designer can appear to sport different features for different customers and different markets at different times with just one chip, thus he can aggregate the demand of different customers and different markets to achieve economies of scale, and of inventory management and control.

Claims

1. A method for utilizing a mega-ASIC comprising the steps of:

(a) providing an integrated circuit substrate having a predefined circuit space and a predefined number of bonding pads; and

(b) providing in the predefined circuit space, an excess of programmably activateable ASIC functional blocks, said excess including more ASIC functional blocks than can be operatively used at one time by the ASIC, the excess of ASIC functional blocks being defined to not count redundant defect-bypassing circuitry, which if provided, is provided for recovering from spot manufacturing defects, where the excess ASIC functional blocks include different I/O blocks and/or different user-feature blocks.

2. The mega-ASIC utilizing method of claim 1 and further comprising:

(c) providing programmable logic circuits for selectively powering a subset of the excess ASIC functional blocks and minimizing power consumed by a deactivated other subset of the excess ASIC functional blocks.

3. The mega-ASIC utilizing method of claim 1 and further comprising:

(c) determining current marketability in one or more market spaces, of different subsets of said, excess of ASIC functional blocks; and

(d) in response to said determining step, activating an operative subset of said excess of ASIC functional blocks that is determined to be currently highly marketable in a given market space.

4. A mega-ASIC comprising:

(a) an integrated circuit substrate having a predefined circuit space and a predefined number of bonding pads; and

(b) an excess of ASIC functional blocks provided in said predefined circuit space, said excess including more ASIC functional blocks than can be operatively used at one time by the ASIC, the excess of ASIC functional blocks being defined to not count redundant defect-bypassing circuits, which if provided, are provided for recovering from spot manufacturing defects, where the excess ASIC functional blocks include different I/O blocks and/or different user-feature blocks.

5. The mega-ASIC of claim 4 and further comprising:

(c) programming logic circuits for activating a selected subset of the excess ASIC functional blocks.

6. The mega-ASIC of claim 4 wherein the excess ASIC functional blocks comprise different I/O blocks including mutually-exclusive I/O blocks.

7. The mega-ASIC of claim 4 wherein the excess and different I/O blocks include a first set of front-end I/O blocks and a second set of, back-end I/O blocks, and where the mega-ASIC further includes:

programmable, block activating/de-activating means capable of selectively activating one or more of the front-end I/O blocks and of selectively activating one or more of the back-end I/O blocks.

8. The mega-ASIC of claim 4 and further comprising:

programmable, block activating/de-activating means capable of selectively activating a subset of one or more of said excess of ASIC functional blocks.

9. The mega-ASIC of claim 8 wherein:

(c.1) said programmable, block activating/de-activating means includes at least one of;

(c.1a) selectively blowable fuses;

(c.1b) selectively close-able anti-fuses;

(c.1c) once-programmable read-only-memory (ROM);

(c.1d) electrically re-programmable nonvolatile memory;

(c.1e) magnetically re-programmable nonvolatile memory;

(c.1f) optically re-programmable nonvolatile memory;

(c.1g) magneto-optically re-programmable nonvolatile memory; and

(c.1h) volatile DRAM, SRAM or other memory devices whose storage data is downloaded from other non-volatile memory devices external to said mega-ASIC before operational use is made of the mega-ASIC.

10. The mega-ASIC of claim 8 wherein:

(c.1) said programmable, block activating/de-activating means is operatively coupled to selectively actuate switches among at least one of;

(c.1a) power providing switches which provide power selectively to a corresponding plurality of said excess of ASIC functional blocks; and

(c.1b) exterior coupling switches which provide coupling selectively between a corresponding plurality to-exterior linking nodes and a corresponding plurality of said excess of ASIC functional blocks.

11. The mega-ASIC of claim 8 wherein:

(c.1) said programmable, block activating/de-activating means is operatively coupled to a buried bonding pad for receiving program data from the buried bonding pad.

12. The mega-ASIC of claim 8 wherein:

(c.1) said programmable, block activating/de-activating means is operatively coupled to a serial testing circuit for receiving program data from the serial testing circuit.

13. The mega-ASIC of claim 8 wherein:

(c.1) said programmable, block activating/de-activating means is operatively coupled to a wireless receiver for receiving configuaration data that is wirelessly transmitted from external programming equipment.

14. The mega-ASIC of claim 13 wherein:

(c.2) the block activating/de-activating means programmed as part of a mass programming operation carried out by a programmer transmitting programming data to a number of units simultaneously.

15. The mega-ASIC of claim 12 wherein:

(c.1a) said serial testing circuit includes decryption circuitry for receiving an encrypted key signal, where proper decryption of the encrypted key signal is required to enable the programmable, block activating/de-activating means to be programmed with configuration data.

16. A method of reducing probability that a mass produced ASIC will lack market-demanded features in a future time space and market space, the method comprising:

(a) cramming more ASIC functionality into a monolithic chip (or chip set) than can probably or definitely be operative at one time when the chip is inserted into a broader, operative circuit, where the excessive ASIC functionality is chosen to anticipate different market development probabilities in a host of different market spaces (e.g., in different countries where different interoperability standards are chosen).

17. Manufactured instructing signals for instructing an instructable machine to carry out a mega-ASIC configuring method for configuring a mega-ASIC comprising:

(0.1) an integrated circuit substrate having a predefined circuit space and a predefined number of bonding pads; and

(0.2) an excess of ASIC functional blocks provided in said predefined circuit space, said excess including more ASIC functional blocks than can be operatively used at one time by the ASIC, the excess of ASIC functional blocks being defined to not count redundant defect-bypassing circuits, which if provided, are provided for recovering from spot manufacturing defects, where the excess ASIC functional blocks include different I/O blocks and/or different user-feature blocks, said manufactured instructing signals comprising;

(a) first signals for designating a subset of said excess of ASIC functional blocks as being activated.

18. A method for selectively programming a large plurality of mega-ASICs comprising:

(a) blanket programming the large plurality of mega-ASICs with first configuration data; and

(b) selectively re-programming a smaller subset of the large plurality of mega-ASICs with different, second configuration data.