Non-volatile memory device and method of programming same
First Claim
1. A method of programming a non-volatile memory device, the method comprising:
- applying a wordline voltage and a bitline voltage to a memory cell of the non-volatile memory device;
detecting whether the bitline voltage falls below a predetermined detection voltage during a first programming period associated with a first program loop; and
, determining programming conditions for a second programming period associated with a second program loop following the first programming loop based on the result of the bitline voltage detection.
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Accused Products
Abstract
Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage during a current program loop, or the bulk voltage becomes higher than a second predetermined detection voltage, the same wordline voltage is used in the current programming loop and a next program loop following the current program loop. Otherwise, the wordline voltage is incremented by a predetermined amount before the next programming loop.
19 Citations
41 Claims
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1. A method of programming a non-volatile memory device, the method comprising:
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applying a wordline voltage and a bitline voltage to a memory cell of the non-volatile memory device;
detecting whether the bitline voltage falls below a predetermined detection voltage during a first programming period associated with a first program loop; and
,determining programming conditions for a second programming period associated with a second program loop following the first programming loop based on the result of the bitline voltage detection. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of programming a non-volatile memory device, the method comprising:
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applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell of the non-volatile memory device;
detecting whether the bulk voltage rises above a predetermined detection voltage during a first programming period associated with a first program loop; and
,determining programming conditions for a second programming period associated with a second program loop following the first program loop based on the result of the bulk voltage detection. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A non-volatile memory device, comprising:
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a first voltage generating circuit generating a first voltage applied to a memory cell in the non-volatile memory device;
a second voltage generating circuit generating a second voltage applied to the memory cell; and
,a control circuit generating a control signal having a logic state that varies in accordance with a determination of the second voltage level in relation to a predetermined detection voltage during a first programming period associated with a first program loop;
wherein the control circuit controls the first voltage generating circuit to generate the first voltage at a first voltage level during a second programming period associated with a second program loop following the first program loop where the second voltage falls below the predetermined detection voltage during the first programming period. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A method of programming a non-volatile memory device, the method comprising:
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performing a plurality of program loops comprising a programming period and a program verification period;
wherein programming conditions for a second program loop following a first program loop are determined in response to a program condition being satisfied in the first program loop. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A non-volatile memory device, comprising:
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a first voltage generating circuit generating a first voltage applied to a memory cell of the non-volatile memory device;
a second voltage generating circuit generating a second voltage applied to the memory cell; and
,a control circuit generating a control signal having a logic state that varies in relation to a level of the second voltage during a first programming period associated with a first program loop;
wherein the control circuit controls the first voltage generating circuit to generate the first voltage at the same level during a second programming period associated with a second program loop following the first program loop in cases where the second voltage rises above the predetermined detection voltage during the first programming period. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41)
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Specification