Method of making a semiconductor structure for high power semiconductor devices

• US 20060088978A1
• Filed: 10/13/2005
• Published: 04/27/2006
• Est. Priority Date: 10/27/2004
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Corporation
• Inventors: Howell, Robert S., Clarke, Rowland C., Aumer, Michael E.
• Granted Patent: US 7,560,322 B2
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/735 Lateral transistors
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A substrate arrangement for high power semiconductor devices includes a SiC wafer having a Si layer deposited on a surface of the SiC wafer. An SOI structure having a first layer of Si, an intermediate layer of SiO₂ and a third layer of Si, has its third layer of Si bonded to the Si deposited on the SiC wafer, forming a unitary structure. The first layer of Si and the intermediate layer of SiO₂ of the SOI are removed, leaving a pure third layer of Si on which various semiconductor devices may be fabricated. The third layer of Si and deposited Si layer may be removed over a portion of the substrate arrangement such that one or more semiconductor devices may be fabricated on the SiC wafer while other semiconductor devices may be accommodated on the pure third layer of Si.

Claims

1. A method of making a semiconductor structure, comprising the steps of:

providing a silicon carbide wafer;

depositing a silicon layer on a surface of said wafer;

providing a silicon on insulator structure having a first layer of silicon, an intermediate layer of an oxide of silicon and a third layer of silicon;

bonding said third layer of silicon to said deposited layer of silicon which is on said surface of said wafer;

removing said first layer of silicon, from said silicon on insulator structure;

removing said intermediate layer of an oxide of silicon, from said silicon on insulator structure to expose said third layer of silicon; and

fabricating at least one semiconductor device on said exposed third layer of silicon.

2. A method according to claim 1 which includes the step of:

selecting said Silicon carbide wafer from the group consisting of polycrystalline cubic silicon carbide and 4H and 6H polytypes.

3. A method according to claim 1 which includes the step of:

selecting said silicon layer from the group consisting of amorphous silicon and polysilicon.

4. A method according to claim 1 wherein the step of bonding comprises:

polishing said third layer of silicon and polishing said deposited layer of silicon which is on said surface of said wafer to a surface roughness of less than around 10 nm; and

bringing said polished surfaces together and applying pressure.

5. A method according to claim 4 which includes the additional step of:

annealing the resulting structure at around 500 to 1100°

C.

6. A method according to claim 1 which includes the steps of:

after said third layer of silicon is exposed, depositing a masking material on a portion of said exposed silicon, leaving an unexposed region;

removing said third layer of silicon and the underlying silicon layer in said unexposed region, to expose a surface of said silicon carbide wafer;

removing said masking material;

fabricating at least one semiconductor device on said exposed silicon carbide wafer surface and fabricating at least one semiconductor device on said exposed third layer of silicon.

7. A method according to claim 6 which includes the steps of:

providing a pure single crystal silicon carbide wafer.

8. A method according to claim 7 which includes the steps of:

providing a pure single crystal silicon carbide wafer selected from the group consisting of 4H and 6H polytypes.