Memory controller and method for optimized read/modify/write performance

• US 20060090044A1
• Filed: 10/21/2004
• Published: 04/27/2006
• Est. Priority Date: 10/21/2004
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hovis, William Paul, Hillier, Philip Rogers III, Kirscht, Joseph Allen
• Granted Patent: US 7,328,317 B2
• Time in Patent Office: Days
• US Class Current: 711/155
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 9/3004 to perform operations on memory

Abstract

A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

Claims

1. A memory controller comprising:

a read queue;

a write queue; and

wherein the memory controller translates a read-modify-write (RMW) command into a read command on the read queue and a write command on the write queue and controls the sequence of executing the read command and the write command.

2. The memory controller of claim 1 wherein the memory controller further comprises a RMW queue to hold the RMW command.

3. The memory controller of claim 2 wherein the memory controller combines a plurality of RMW commands in the RMW queue that modify the same cacheline.

4. The memory controller of claim 2 wherein the memory controller removes the RMW command from the RMW queue after receiving the results of executing the read command, and writes the write command to the write queue.

5. The memory controller of claim 1 wherein the write queue has a dependency indicator for the RMW command in the write queue.

6. The memory controller of claim 1 wherein a read command on the read queue may be executed after commencing a read portion of a RMW cycle and before completion of the RMW cycle.

7. The memory controller of claim 1 wherein the memory controller combines RMW commands that write to the same cacheline into a full cacheline write command and moves the full cacheline write command to the write queue.

8. The memory controller of claim 1 wherein the memory is embedded memory.

9. A memory controller comprising:

a write queue for write operations to a memory coupled to the memory controller;

a read queue for read operations to the memory;

a RMW queue for RMW operations to the memory;

in response to a RMW command issued to the memory controller, the memory controller performing the steps of;

writing a read command portion of the RMW command to the read queue;

waiting for data from the executing read command portion of the RMW command;

combining the data from the read command portion of the RMW command with partial data from the RMW command into a single write command; and

writing the single write command to the write queue.

10. The memory controller of claim 9 wherein the memory controller further performs the step of combining entries in the RMW queue that access the same cacheline.

11. The memory controller of claim 9 wherein the memory controller further performs the step of combining an entry on the RMW queue with an entry on the write queue to the same cacheline into the entry on the write queue.

12. The memory controller of claim 9 wherein a read command on the read queue may be executed after commencing a read portion of a read-modify-write cycle and before completion of the read-modify-write cycle.

13. The memory controller of claim 9 wherein a read command on the read queue may be executed after commencing a read portion of a read-modify-write cycle and before completion of the read-modify-write cycle.

14. A method for a memory controller to access memory, the method comprising the steps of:

writing a read command to a read queue;

writing a write command to a write queue;

translating a RMW command into a read command on the read queue and a write command on the write queue; and

controlling the sequence of executing the read command and the write command.

15. The method of claim 14, further comprising the step of writing a RMW command to a RMW queue.

16. The method of claim 15, further comprising the step of combining a plurality of RMW commands in the RMW queue that modify the same cacheline.

17. The method of claim 15, further comprising the step of removing the RMW command from the RMW queue after receiving the results of the executing read command and writing the write command to the write queue.

18. The method of claim 14, further comprising the step of setting a dependency indicator for the RMW command in the write queue.

19. The method of claim 14, wherein a read command on the read queue is executed after commencing a read portion of a read-modify-write cycle and before completion of the read-modify-write cycle.

20. The method of claim 14, further comprising the step of combining RMW commands that write to the same cacheline into a full cacheline write and clearing a RMW command flag.

21. A method for a memory controller to access memory, the method comprising the steps of:

writing a read command to a read queue;

writing a write command to a write queue;

writing a RMW command to a RMW queue;

writing a read command portion of the RMW command to the read queue;

waiting for data from the executing read command portion of the RMW command;

combining the data from the read command portion of the RMW command with partial data from the RMW command into a single write command; and

writing the single write command to the write queue.

22. The memory controller of claim 21 wherein the memory controller further performs the step of combining entries in the RMW queue that access the same cacheline.

23. The memory controller of claim 21 wherein the memory controller further performs the step of combining an entry on the RMW queue with an entry on the write queue to the same cacheline into the entry on the write queue.

24. The memory controller of claim 21 wherein a read command on the read queue may be executed after commencing a read portion of a read-modify-write cycle and before completion of the read-modify-write cycle.