Reconfigurable processor

• US 20060090062A1
• Filed: 01/20/2003
• Published: 04/27/2006
• Est. Priority Date: 01/19/2002
• Status: Active Grant

• Current Assignee: Maren Krass, Thomas Richter
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin, Baumgarte, Volker
• Granted Patent: US 8,281,108 B2
• Time in Patent Office: Days
• US Class Current: 712/226
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A processor includes a reconfigurable field of data processing cells. A register is provided where the register has a data stream memory designed to store a data stream and/or parts thereon. The register may be a RAM PAE.

Claims

1-6. -6. (canceled)

7. A processor, comprising:

a reconfigurable field of data processing cells; and

a register, wherein the register has a data stream memory designed to store at least one of a data stream and parts of the data stream.

8. The processor as recited in claim 7, further comprising:

at least one;

i) of a register allocation device to allocate the register, and ii) a register releasing device to release the register.

9. The processor as recited in claim 8, wherein the register allocation device is configured to be preserved over multiple reconfigurations of the reconfigurable field of data processing cells.

10. The processor as recited in claim 7, wherein the register is a RAM PAE.

11. The processor as recited in claim 7, further comprising:

a second register configured to provide read and write access when a virtual FIFO dividing line is implemented.

12. The processor as recited in claim 7, further comprising:

at least one memory unit configured for use as a stack and being configured to indicate at least one of a stack underflow state and a stack overflow state.

13. The processor as recited in claim 12, wherein the at least one measuring unit is configured to indicate the at least one of the underflow state and overflow state of an operating system unit.