Asymetric layout structures for transistors and methods of fabricating the same

• US 20060091498A1
• Filed: 10/29/2004
• Published: 05/04/2006
• Est. Priority Date: 10/29/2004
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Henning, Jason, Sriram, Saptharishi
• Granted Patent: US 7,265,399 B2
• Time in Patent Office: Days
• US Class Current: 257/578
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66863 Lateral single gate transistors
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802

Abstract

High power transistors are provided. The transistors include a source region, a drain region and a gate contact. The gate contact is positioned between the source region and the drain region. First and second ohmic contacts are provided on the source and drain regions, respectively. The first and second ohmic contacts respectively define a source contact and a drain contact. The source contact and the drain contact have respective first and second widths. The first and second widths are different. Related methods of fabricating transistors are also provided.

Claims

1. A unit cell of a high power transistor comprising:

a transistor having a source region, a drain region and a gate contact, the gate contact being between the source region and the drain region; and

first and second ohmic contacts on the source and drain regions, respectively, that respectively define a source contact and a drain contact, the source contact and the drain contact having respective first and second widths, wherein the first width and the second width are different.

2. The unit cell of claim 1, wherein the first width is less than an average width of the first and second widths and the second width is greater than the average width of the first and second widths.

3. The unit cell of claim 1, wherein the second width is less than an average width of the first and second widths and the first width is greater than the average width of the first and second widths.

4. The unit cell of claim 1, wherein the source region and the drain region have respective third and fourth widths and wherein the third and fourth widths are different.

5. The unit cell of claim 1, wherein the source contact and the source region are split into first and second portions such that a portion of a surface of a first epitaxial layer is not disposed beneath the source contact or the source region or the drain contact and the drain region are split into first and second portions such that a portion of the surface of the first epitaxial layer is not disposed beneath the drain contact or the drain region.

6. The unit cell of claim 1, wherein the source contact is split into at least first and second portions such that a portion of a surface of the source region is not disposed beneath the source contact.

7. The unit cell of claim 1, wherein the drain contact is split into at least first and second portions such that a portion of a surface of the drain region is not disposed beneath the drain contact.

8. The unit cell of claim 1, wherein the transistor comprises a metal semiconductor field effect transistor (MESFET).

9. The unit cell of claim 8, wherein the MESFET comprises a silicon carbide (SiC) MESFET, a gallium arsenide (GaAs) MESFET or a gallium Nitride (GaN) HEMT.

10. A unit cell of a high power transistor comprising:

a transistor having a source region, a drain region and a gate contact, the gate contact being between the source region and the drain region; and

first and second ohmic contacts on the source and drain regions, respectively, that respectively define a source contact and a drain contact, wherein the source contact is split into first and second portions such that a portion of a surface of a first epitaxial layer is not disposed beneath the source contact or wherein the drain contact is split into first and second portions such that a portion of the surface of the first epitaxial layer is not disposed beneath the drain contact.

11. The unit cell of claim 10, wherein the source contact is split into at least first and second portions such that a portion of a surface of the source region is not disposed beneath the source contact or wherein the drain contact is split into at least first and second portions such that a portion of a surface of the drain region is not disposed beneath the drain contact.

12. The unit cell of claim 10, wherein the source contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first width is less than an average of the first and second widths and wherein the second width is greater than the average of the first and second widths.

13. The unit cell of claim 10, wherein the source contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first width is greater than an average of the first and second widths and wherein the second width is less than the average of the first and second widths

14. The unit cell of claim 10, wherein the source contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first and second widths are equal.

15. The unit cell of claim 10, wherein the drain contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first width is less than an average of the first and second widths and wherein the second width is greater than the average of the first and second widths.

16. The unit cell of claim 10, wherein the drain contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first width is greater than an average of the first and second widths and wherein the second width is less than the average of the first and second widths

17. The unit cell of claim 10, wherein the drain contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first and second widths are equal.

18. The unit cell of claim 10, wherein the transistor comprises a metal semiconductor field effect transistor (MESFET).

19. The unit cell of claim 18, wherein the MESFET comprises a silicon carbide (SiC) MESFET, a gallium arsenide (GaAs) MESFET or a gallium Nitride (GaN) HEMT.

20. A high power transistor comprising:

a plurality of unit cells each having a source region and a drain region;

a plurality of gate electrodes of the unit cells, ones of the plurality of gate electrodes being between the source region and the drain region of the unit cells;

a plurality of source electrodes on the source regions of the unit cells; and

a plurality of drain electrodes on the drain regions of the unit cells, the plurality of source electrodes and the plurality of drain electrodes having respective first and second widths, wherein the first width is less than an average width of the first and second widths and the second width is greater than the average width of the first and second widths.

21. A high power transistor comprising:

a plurality of unit cells each having a source region and a drain region;

a plurality of gate electrodes of the unit cells, ones of the plurality of gate electrodes being between the source region and the drain region of the unit cells;

a plurality of source electrodes on the source regions of the unit cells; and

a plurality of drain electrodes on the drain regions of the unit cells, wherein the plurality of source electrodes are split into at least first and second portions such that a portion of a surface of a first epitaxial layer is not disposed beneath the source electrodes or wherein the plurality of drain contacts and the plurality of drain regions are split into at least first and second portions such that a portion of the surface of the first epitaxial layer is not disposed beneath the source electrodes.

22. A method of forming a unit cell of a high power transistor comprising:

forming a transistor having a source region, a drain region and a gate contact, the gate contact being between the source region and the drain region; and

forming first and second ohmic contacts on the source and drain regions, respectively, that respectively define a source contact and a drain contact, the source contact and the drain contact having respective first and second widths, wherein the first and second widths are different.

23. The method of claim 22, wherein the first width is less than an average width of the first and second widths and the second width is greater than the average width of the first and second widths.

24. The method of claim 22, wherein the first width is narrower than the second width, wherein the first width is from about 10 to about 20 μ

m and wherein the second width is from about 25 to about 35 μ

m.

25. The method of claim 22, wherein the second width is narrower than the first width, wherein the second width is from about 10 to about 15 μ

m and wherein the second width is from about 25 to about 35 μ

m.

26. The method of claim 22, wherein the source region and the drain region have respective third and fourth widths and wherein the third and fourth widths are different.

27. The method of claim 22, wherein the source contact and the source region are split into first and second portions such that a portion of a surface of a first epitaxial layer is not disposed beneath the source contact or the source region or the drain contact and the drain region are split into first and second portions such that a portion of the surface of the first epitaxial layer is not disposed beneath the drain contact or the drain region.

28. The method of claim 22, wherein the source contact is split into at least first and second portions such that a portion of a surface of the source region is not disposed beneath the source contact.

29. The method of claim 22, wherein the drain contact is split into at least first and second portions such that a portion of a surface of the drain region is not disposed beneath the drain contact.

30. The method of claim 22, wherein forming the transistor comprises forming a metal semiconductor field effect transistor (MESFET).

31. The method of claim 30, wherein forming the MESFET comprises forming a silicon carbide (SiC) MESFET, a gallium arsenide (GaAs) MESFET or a gallium Nitride (GaN) HEMT.

32. A method of forming a unit cell of a high power transistor comprising:

forming a transistor having a source region, a drain region and a gate contact, the gate contact being between the source region and the drain region; and

forming first and second ohmic contacts on the source and drain regions, respectively, that respectively define a source contact and a drain contact, wherein the source contact is split into at least first and second portions such that a portion of a surface of a first epitaxial layer is not disposed beneath the source contact or wherein the drain contact is split into at least first and second portions such that a portion of the surface of the first epitaxial layer is not disposed beneath the drain contact.

33. The method of claim 32, wherein the source contact is split into at least first and second portions such that a portion of a surface of the source region is not disposed beneath the source contact or wherein the drain contact is split into at least first and second portions such that a portion of a surface of the drain region is not disposed beneath the drain contact.

34. The method of claim 32, wherein the source contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first width is less than an average of the first and second widths and wherein the second width is greater than the average of the first and second widths.

35. The method of claim 32, wherein the source contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first width is greater than an average of the first and second widths and wherein the second width is less than the average of the first and second widths

36. The method of claim 32, wherein the source contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first and second widths are equal.

37. The method of claim 32, wherein the drain contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first width is less than an average of the first and second widths and wherein the second width is greater than the average of the first and second widths.

38. The method of claim 32, wherein the drain contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first width is greater than an average of the first and second widths and wherein the second width is less than the average of the first and second widths

39. The method of claim 32, wherein the drain contact is split, wherein the source and drain contacts have respective first and second widths, wherein the first and second widths are equal.

40. The method of claim 32, wherein forming the transistor comprises forming a metal semiconductor field effect transistor (MESFET).

41. The method of claim 40, wherein forming the MESFET comprises forming a silicon carbide (SiC) MESFET, a gallium arsenide (GaAs) MESFET or a gallium Nitride (GaN) HEMT.

42. A method of forming a high power transistor comprising:

forming a plurality of unit cells each having a source region and a drain region;

forming a plurality of gate electrodes of the unit cells, ones of the plurality of gate electrodes being between the source region and the drain region of the unit cells;

forming a plurality of source electrodes on the source regions of the unit cells; and

forming a plurality of drain electrodes on the drain regions of the unit cells, the plurality of source electrodes and the plurality of drain electrodes having respective first and second widths, wherein the first width is less than an average width of the first and second widths and the second width is greater than the average width of the first and second widths.

43. A method of forming a high power transistor comprising:

forming a plurality of unit cells each having a source region and a drain region;

forming a plurality of gate electrodes of the unit cells, ones of the plurality of gate electrodes being between the source region and the drain region of the unit cells;

forming a plurality of source electrodes on the source regions of the unit cells; and

forming a plurality of drain electrodes on the drain regions of the unit cells, wherein the plurality of source electrodes are split into at least first and second portions such that a portion of a surface of a first epitaxial layer is not disposed beneath the source electrodes or wherein the plurality of drain contacts are split into at least first and second portions such that a portion of the surface of the first epitaxial layer is not disposed beneath the drain electrodes.

44. A method of designing a transistor comprising:

increasing a first width of a source contact by an amount such that the first width is greater than an average width of the first and a second width;

decreasing the second width of a drain contact by the amount such that the second width is less than the average width; and

fabricating the source an drain contacts having the first and second widths, respectively.