Methods and computer program products for determining simultaneous switching induced data output timing skew

• US 20060092717A1
• Filed: 08/01/2005
• Published: 05/04/2006
• Est. Priority Date: 10/23/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Kwang-il, Jang, Seong-jin, Song, Ho-young
• Granted Patent: US 7,558,979 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device. The memory device is read to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device. Timing skew is determined between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device.

Claims

1. A method of determining timing skew between data outputs of a memory device comprising:

writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device;

reading the memory device to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device; and

determining timing skew between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device.

2. A method according claim 1 wherein the predetermined data pattern is selected to generate delay in reading the memory device due to switching of voltage levels at the outputs of the memory device.

3. A method according to claim 2 wherein determining timing skew between outputs from the memory device comprises:

setting a minimum delay time estimated to be when data would be output from the memory device without the delay due to switching;

measuring an output time when the predetermined data becomes valid at the outputs; and

determining the delay by subtracting the minimum delay time from the output time.

4. A method according to claim 1 wherein determining timing skew between outputs comprises determining the timing skew for each output of the memory.

5. A data training method performed in a memory device which does not include an additional device for data training, the method comprising:

(a) writing a predetermined data pattern to the memory device;

(b) reading a data pattern from the memory device; and

(c) determining a delay time in data transmission by measuring a delay time between the read data pattern and the predetermined data pattern,

wherein a speed at which the predetermined data pattern is written to the memory device is less than a normal operating speed of the memory device, and

a speed at which the data pattern is read from the memory device is equivalent to the normal operating speed of the memory device.

6. The data training method of claim 5, wherein (a) the writing of the predetermined data pattern comprises:

(a1) operating the memory device at a frequency less than a normal operating frequency of the memory device; and

(a2) writing the predetermined data pattern to a predetermined cell of the memory device.

7. The data training method of claim 5, wherein (b) the reading of the data pattern comprises:

(b1) operating the memory device at the normal operating frequency; and

(b2) reading the data pattern from the memory device at the normal operating frequency.

8. The data training method of claim 7, wherein (b) the reading of the data pattern further comprises (b2) selecting a pin of the memory device which performs data training.

9. The data training method of claim 8, wherein (b) the reading of the data pattern further comprises (b3) setting a minimum delay time in data transmission.

10. The data training method of claim 9, wherein (c) the determining of the delay time in data transmission comprises:

(c1) measuring a delay time between the read data pattern and the predetermined data pattern;

(c2) determining the delay time in data transmission using the measured delay time and the minimum delay time; and

(c3) storing the determined delay time, and selecting another pin of the memory device when it is determined that all pins of the memory device are not checked.

11. A computer program product for determining timing skew between data outputs of a memory device comprising a computer readable medium having computer readable program code embodied therein, the computer readable program product comprising:

computer readable program code configured to write a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device;

computer readable program code configured to read the memory device to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device;

computer readable program code configured to determine timing skew between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device.

12. A computer program product according claim 11 wherein the predetermined data pattern is selected to generate delay in reading the memory device due to switching of voltage levels at the outputs of the memory device.

13. A computer program product according to claim 12 wherein the computer readable program code configured to determine timing skew between outputs from the memory device comprises:

computer readable program code configured to set a minimum delay time estimated to be when data would be output from the memory device without the delay due to switching;

computer readable program code configured to measure an output time when the predetermined data becomes valid at the outputs; and

computer readable program code configured to determine the delay by subtracting the minimum delay time from the output time.

14. A computer program product according to claim 11 wherein the computer readable program code configured to determine timing skew between outputs comprises computer readable program code configured to determine the timing skew for each output of the memory.

15. A method of determining timing skew between data outputs of a memory device comprising:

determining timing skew between outputs from the memory device based on a difference between the actual time when predetermined data is provided from the memory device and a minimum delay time.

16. A method according to claim 15 wherein the predetermined data is written to the memory device at a relatively slow speed in comparison to a speed at which the predetermined data is read from the memory device.