Method and apparatus for varying energy per instruction according to the amount of available parallelism

• US 20060095807A1
• Filed: 09/28/2004
• Published: 05/04/2006
• Est. Priority Date: 09/28/2004
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intel Corporation
• Inventors: Shen, John, Wang, Hong, Orenstein, Doron, Ronen, Ronny, Grochowski, Edward, Sheaffer, Gad S., Annavaram, Murali M.
• Granted Patent: US 7,437,581 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the various cores. If the amount of parallelism is high, then the processor may be configured to run a larger amount of threads on cores configured to consume less power. If the amount of parallelism is low, then the processor may be configured to run a smaller amount of threads on cores configured for greater scalar performance.

Claims

18. A processor, comprising:

a first plurality of a first type of cores;

a second plurality of a second type of cores; and

a module to allocate a thread to one of either said first plurality of said first type of cores or said second plurality of said second type of cores.

19. The processor of claim 18, wherein said module to allocate said thread according to a power budget.

20. The processor of claim 18, wherein said module to allocate said thread according to an allocation table.

21. The processor of claim 18, wherein said module includes a thread migration logic to allocate a new thread to one of said second plurality of cores and to migrate an existing thread from one of said first plurality of cores to one of said second plurality of cores.

22. The processor of claim 21, wherein said thread migration logic includes a table for mapping logical cores to physical cores.

23. The processor of claim 21, wherein said thread migration logic is responsive to an operating system scheduler.

24. The processor of claim 18, wherein said first type of cores have higher performance than said second type of cores by design.

25. The processor of claim 18, wherein said first type of cores have higher performance than said second type of cores by configuration.

26. A method, comprising:

allocating a set of threads to a set of processor cores;

monitoring a consumed power of said processor cores;

computing an error value between said consumed power and a desired power; and

transitioning from said allocation based on said error value.

27. The method of claim 26, wherein said transitioning includes changing said allocation of said set of threads among more powerful cores and less powerful cores in said set of processor cores.

28. The method of claim 26, wherein said transitioning includes changing said allocation of said set of threads among more powerful cores and less powerful cores by configuring said more powerful cores and said less powerful cores in said set of processor cores.

29. The method of claim 26, further comprising integrating said error value over time.

30. The method of claim 26, further comprising sampling said error value over time.

31. A method, comprising:

determining a set of running threads; and

allocating each of said threads to one of a set of processor cores, wherein said allocating is responsive to a power budget.

32. The method of claim 31, wherein said set of processor cores includes configurable cores capable of acting as cores of a first type and of a second type.

33. The method of claim 31, wherein said set of processor cores includes cores designed as cores of a first type and of a second type.

34. The method of claim 31, further comprising allocating a new thread to a core of a second type from said set of processor cores, and migrating one of said set of running threads from a core of a first type to a core of said second type in said set of processor cores.

35. The method of claim 34, wherein said migrating is performed by thread migration logic.

36. The method of claim 34, wherein said migrating is responsive to an operating system scheduler.

37. A system, comprising:

a processor including a monitor logic to monitor a value of an attribute of a core of said processor, a convert logic to determine a measure of power consumption of said processor responsive to said attribute of said core, and a control logic to adjust an energy per instruction metric of said processor responsive to said measure of power consumption;

an audio input-output logic; and

an interface to couple said processor to said audio input-output logic.

1. A processor, comprising:

a monitor logic to monitor a value of an attribute of a core of said processor;

a convert logic to determine a measure of power consumption of said processor responsive to said attribute of said core; and

a control logic to adjust an energy per instruction metric of said processor responsive to said measure of power consumption.

4. The processor of claim 1, wherein said attribute of said core is the number of instructions retired per clock.

5. The processor of claim 4, wherein said measure of power consumption is determined by multiplying said number of instructions retired per clock by the amount of energy expended per instruction per clock.

6. The processor of claim 1, wherein said attribute of said core is active status of a functional block of said core.

7. The processor of claim 6, wherein said measure of power consumption is determined by multiplying said active status of said functional block by the amount of energy expended per clock when said functional block is in said active status.

8. The processor of claim 1, wherein said attribute is a core supply current.

9. The processor of claim 8, wherein said measure of power consumption includes said core supply current.

10. The processor of claim 1, wherein said control logic to adjust an operating voltage and an operating frequency of said processor responsive to said measure of power consumption.

11. The processor of claim 1, wherein said control logic to migrate threads of a program between large cores and small cores of said processor responsive to said measure of power consumption.

12. The processor of claim 1, wherein said control logic to turn on optional performance circuitry in said core of said processor responsive to said measure of power consumption.

13. The processor of claim 1, wherein said control logic to turn on optional speculation circuitry in said core of said processor responsive to said measure of power consumption.

14. The processor of claim 1, further comprising difference logic to compute a difference between said measure of power consumption and a desired power consumption.

15. The processor of claim 14, further comprising integrating circuitry to determine a time integral of said difference between said measure of power consumption and a desired power consumption.

16. The processor of claim 14, further comprising sampling circuitry to supply said measure of power consumption to said control logic according to a sampling method.

17. The processor of claim 1, further comprising a clock throttle circuit to permit fast feedback control.

38. The system of claim 37, wherein said attribute of said core is a core running state, and wherein said measure of power consumption is determined by multiplying said core running state by the amount of energy expended per clock when said core is in said core running state.

39. The system of claim 37, wherein said attribute of said core is the number of instructions retired per clock, and wherein said measure of power consumption is determined by multiplying said number of instructions retired per clock by the amount of energy expended per instruction per clock.

40. The system of claim 37, wherein said attribute of said core is active status of a functional block of said core, and wherein said measure of power consumption is determined by multiplying said active status of said functional block by the amount of energy expended per clock when said functional block is in said active status.

41. The system of claim 37, wherein said attribute is a core supply current, and wherein said measure of power consumption includes said core supply current.

42. The system of claim 37, wherein said control logic to adjust an operating voltage and an operating frequency of said processor responsive to said measure of power consumption.

43. The system of claim 37, wherein said control logic to migrate threads of a program between large cores and small cores of said processor responsive to said measure of power consumption.

44. The system of claim 37, wherein said control logic to turn on optional performance circuitry in said core of said processor responsive to said measure of power consumption.

45-1. The system of claim 37, wherein said processor further comprises difference logic to compute a difference between said measure of power consumption and a desired power consumption.

45-2. The system of claim 45, wherein said processor further comprises integrating circuitry to determine a time integral of said difference between said measure of power consumption and a desired power consumption.

47. A system, comprising:

a processor including a first plurality of a first type of cores, a second plurality of a second type of cores, and a module to allocate a thread to one of either said first plurality of said first type of cores or said second plurality of said second type of cores;

an audio input-output logic; and

an interface to couple said processor to said audio input-output logic.

48. The system of claim 47, wherein said module to allocate said thread according to a power budget.

49. The system of claim 47, wherein said module to allocate said thread according to an allocation table.

50. The system of claim 47, wherein said module includes a thread migration logic to allocate a new thread to one of said second plurality of cores and to migrate an existing thread from one of said first plurality of cores to one of said second plurality of cores.

51. The system of claim 50, wherein said thread migration logic includes a table for mapping logical cores to physical cores.

52-3. The processor of claim 52, wherein said means for transitioning includes means for changing said allocation of said set of threads among more powerful cores and less powerful cores in said set of processor cores.

56. A processor, comprising:

means for determining a set of running threads; and

means for allocating each of said threads to one of a set of processor cores, wherein said allocating is responsive to a power budget.

57. The processor of claim 56, wherein said set of processor cores includes configurable cores capable of acting as cores of a first type and of a second type.

58. The processor of claim 56, wherein said set of processor cores includes cores designed as cores of a first type and of a second type.

59. The processor of claim 56, further comprising means for allocating a new thread to a core of a second type from said set of processor cores, and means for migrating one of said set of running threads from a core of a first type to a core of said second type in said set of processor cores.