Wireless node providing improved battery power consumption and system employing the same

• US 20060100002A1
• Filed: 12/21/2005
• Published: 05/11/2006
• Est. Priority Date: 10/15/2003
• Status: Active Grant

• Current Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Luebke, Charles J., Senn, Jeffrey A.
• Granted Patent: US 7,831,282 B2
• Time in Patent Office: Days
• US Class Current: 455/574
• CPC Class Codes: B63G 8/00 Underwater vessels, e.g. submarines; Equipment specially adapted thereforsubmarine hulls B63B3/13; diving chambers with mechanical link, e.g. cable, to a base B63C11/34; divers' sleds B63C11/46; torpedoes F42B19/00
• CPC Class Codes: G06F 3/0362 with detection of 1D translations or rotations of an operating part of the device, e.g. scroll wheels, sliders, knobs, rollers or belts
• CPC Class Codes: G06F 3/0481 based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance
• CPC Class Codes: H04L 12/2803 Home automation networks
• CPC Class Codes: H04L 12/2823 Reporting information sensed by appliance or service execution status of appliance services in a home automation network device-related reporting H04L43/065; arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom H04Q9/00
• CPC Class Codes: H04L 2012/2841 Wireless
• CPC Class Codes: H04L 2012/285 Generic home appliances, e.g. refrigerators
• CPC Class Codes: H04L 67/02 based on web technology, e.g. hypertext transfer protocol [HTTP]
• CPC Class Codes: H04L 67/04 specially adapted for terminals or networks with limited capabilities; specially adapted for terminal portability
• CPC Class Codes: H04L 67/125 involving control of end-device applications over a network
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: H04W 84/12 WLAN [Wireless Local Area Networks]
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A system includes fobs and sensors each of which has a wireless transceiver, a processor and a battery powering the transceiver and processor. A server includes a processor and wireless transceiver, both of which are mains-powered. A fob processor timer repetitively causes its processor to enter a normal mode from a sleep mode, cause the transceiver to enter a powered state from a reduced power state, and send a wireless message from its transceiver to the server transceiver to request data therefrom. A sensor processor timer repetitively causes its processor to enter a normal mode from a sleep mode, cause the transceiver to enter a powered state from a reduced power state, read an analog or digital input, and send a wireless message based upon the read input from its transceiver to the server transceiver to provide data thereto. Each of the timers times asynchronously with respect to other timers.

Claims

1. A wireless node comprising:

a processor comprising a sleep routine, a wakeup routine and an output;

a wireless transceiver comprising an input electrically connected to said output; and

a battery structured to power said processor and said wireless transceiver,

wherein said sleep routine is structured to output a signal on said output to power down said wireless transceiver through said input and place said processor in a sleep mode, in order to minimize power consumption from said battery by said processor and said wireless transceiver, and

wherein said wakeup routine is structured to remove said processor from said sleep mode independent of said wireless receiver.

2. The wireless node of claim 1 wherein said wireless node is a sensor.

3. The wireless node of claim 1 wherein said wireless node is a fob.

4. The wireless node of claim 1 wherein said processor further comprises a display and cooperates with said wireless transceiver to receive a wireless message from another node and update said display based upon said received wireless message.

5. The wireless node of claim 1 wherein the output of said processor is a first output;

wherein said signal is a first signal;

wherein the input of said wireless transceiver is a first input;

wherein said processor further comprises a serial communications interface and a second output; and

wherein said wireless transceiver further comprises a serial communications interface electrically connected to the serial communications interface of said processor, and a second input electrically connected to said second output, said wakeup routine being structured to output a second signal on said first output to power up said wireless transceiver through said first input, output a third signal on said second output to reset said wireless transceiver through said second input, and reinitialize said wireless transceiver through said serial communications interface, in order to resume normal power consumption from said battery by said processor and said wireless transceiver and normal wireless communication through said wireless transceiver.

6. The wireless node of claim 5 wherein said processor further comprises a user input device;

and wherein said wakeup routine is further structured to respond to activity on said user input device to remove said processor from said sleep mode, output said second signal, output said third signal and reinitialize said wireless transceiver.

7. The wireless node of claim 5 wherein said processor further comprises a timer;

and wherein said wakeup routine is further structured to respond to time out of said timer to remove said processor from said sleep mode, output said second signal, output said third signal and reinitialize said wireless transceiver.

8. The wireless node of claim 2 wherein said processor further comprises an analog or digital input and is further structured to cooperate with said wireless transceiver to send a wireless message to another node based upon said analog or digital input.

9. The wireless node of claim 5 wherein said processor further comprises an analog or digital input and is further structured to cooperate with said wireless transceiver to send a wireless message to another node based upon said analog or digital input;

and wherein said wakeup routine is further structured to determine a change of state of said analog or digital input, determine the current state of said analog or digital input, and send said wireless message to said other node based upon said current state.

10. The wireless node of claim 9 wherein said processor further comprises a routine structured to receive an acknowledge wireless message from said other node and responsively cooperate with said sleep routine to output said first signal on said first output to power down said wireless transceiver through said first input and place said processor in said sleep mode, in order to minimize power consumption from said battery by said processor and said wireless transceiver.

11. The wireless node of claim 9 wherein said wakeup routine is further structured to process an interrupt responsive to said change of state of said analog or digital input.

12. The wireless node of claim 9 wherein said wakeup routine is further structured to determine if said change of state of said analog or digital input is a valid state change.

13. The wireless node of claim 9 wherein said processor further comprises a timer;

and wherein said wakeup routine is further structured to respond to time out of said timer.

14. The wireless node of claim 13 wherein the timeout of said timer occurs a predetermined time after said sleep routine places said processor in said sleep mode.

15. The wireless node of claim 13 wherein said wakeup routine is further structured to repetitively read said analog or digital input, and send a wireless message to said other node based upon said read analog or digital input.

16. The wireless node of claim 15 wherein said processor further comprises a routine structured to receive an acknowledge wireless message from said other node and responsively cooperate with said sleep routine to output said first signal on said first output to power down said wireless transceiver through said first input and place said processor in said sleep mode, in order to minimize power consumption from said battery by said processor and said wireless transceiver.

17. The wireless node of claim 13 wherein said wakeup routine is further structured to process an interrupt responsive to said time out of said timer.

18. A wireless node comprising:

a processor comprising a normal mode, a sleep mode and a display;

a wireless transceiver comprising a powered state and a reduced power state; and

a battery structured to power said processor and said wireless transceiver,

wherein said processor is structured to cause said wireless transceiver to enter said reduced power state from said powered state before said processor enters said sleep mode from said normal mode, and

wherein said processor is further structured to cause said wireless transceiver to enter said powered state from said reduced powered state after said processor enters said normal mode from said sleep mode.

19. The wireless node of claim 18 wherein said processor further comprises a timer and a user input device, said processor being further structured to cause said wireless transceiver to enter said reduced power state responsive to no input from said user input device for a first predetermined time, and enter said normal mode responsive to timeout of said timer after a second predetermined time.

20. The wireless node of claim 19 wherein said processor is further structured, after causing said wireless transceiver to enter said powered state, to cause said wireless transceiver to transmit a first message and receive a second message, and update said display responsive to said second message.

21. The wireless node of claim 20 wherein said processor is further structured, after updating said display, to cause said wireless transceiver to enter said reduced power state from said powered state before said processor enters said sleep mode from said normal mode.

22. A wireless node comprising:

a processor comprising a normal mode, a sleep mode, a wakeup routine, and an analog or digital input;

a wireless transceiver comprising a powered state and a reduced power state; and

a battery structured to power said processor and said wireless transceiver,

wherein said processor is structured to cause said wireless transceiver to enter said reduced power state from said powered state before said processor enters said sleep mode from said normal mode,

wherein said wakeup routine is structured to remove said processor from said sleep mode independent of said wireless receiver, and

wherein said processor is further structured to cause said wireless transceiver to enter said powered state from said reduced powered state after said processor enters said normal mode from said sleep mode.

23. The wireless node of claim 22 wherein said processor further comprises a timer structured to cause said processor to enter said normal mode from said sleep mode after a predetermined time;

and wherein said processor is further structured, after causing said wireless transceiver to enter said powered state, to read said analog or digital input and cause said wireless transceiver to transmit a message based upon said read analog or digital input.

24. The wireless node of claim 23 wherein said processor is further structured, after transmitting said message, to cause said wireless transceiver to enter said reduced power state, restart said timer for said predetermined time and enter said sleep mode.

25. The wireless node of claim 24 wherein said processor is further structured to enter said normal mode from said sleep mode responsive to a change of said analog or digital input before causing said wireless transceiver to enter said powered state from said reduced powered state.

26. A system comprising:

at least one fob comprising;

a first wireless transceiver,

a first processor including a first timer, a normal mode, a sleep mode and a display, and

a first battery structured to power said first wireless transceiver and said first processor;

at least one sensor comprising;

a second wireless transceiver,

a second processor including a second timer, a normal mode, a sleep mode, and an analog or digital input, and

a second battery structured to power said second wireless transceiver and said second processor; and

a server comprising a third processor and a third wireless transceiver, said third processor and said third wireless transceiver being mains-powered,

wherein said first timer of a corresponding one of said at least one fob is structured to repetitively cause said first processor to enter said normal mode from said sleep mode, cause said first wireless transceiver to enter said powered state from said reduced power state, and send a first wireless message from said first wireless transceiver to said third wireless transceiver to request first data from said server,

wherein said second timer of a corresponding one of said at least one sensor is structured to repetitively cause said second processor to enter said normal mode from said sleep mode, cause said second wireless transceiver to enter said powered state from said reduced power state, read said analog or digital input, and send a second wireless message based upon said read analog or digital input from said second wireless transceiver to said third wireless transceiver to provide second data to said server, and

wherein each of said first timer and said second timer times asynchronously with respect to the other ones of said first and second timers.