Prefetch miss indicator for cache coherence directory misses on external caches
First Claim
1. A method for reducing latency associated with cache coherence directory misses on external caches in a shared distributed memory data processing system, comprising:
- evaluating a cache coherence directory for possible prefetching of a directory entry into a directory cache;
setting a prefetch miss indicator in response to said prefetch evaluation resulting in a directory miss;
consulting said prefetch miss indicator during subsequent processing of a memory request corresponding to said directory entry; and
taking an accelerated snoop response action based on said prefetch miss indicator being set.
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Abstract
A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache coherence directory is evaluated for possible prefetching of a directory entry into a directory cache. A prefetch miss indicator is set if the prefetch evaluated results in a directory miss. The prefetch miss indicator is consulted during subsequent processing of a memory block request corresponding to the directory entry. An accelerated snoop response action is taken if the prefetch miss indicator is set. The latency of a second lookup into the cache coherence directory, which would otherwise be required, is thereby avoided.
44 Citations
31 Claims
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1. A method for reducing latency associated with cache coherence directory misses on external caches in a shared distributed memory data processing system, comprising:
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evaluating a cache coherence directory for possible prefetching of a directory entry into a directory cache;
setting a prefetch miss indicator in response to said prefetch evaluation resulting in a directory miss;
consulting said prefetch miss indicator during subsequent processing of a memory request corresponding to said directory entry; and
taking an accelerated snoop response action based on said prefetch miss indicator being set. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A directory-based cache coherence controller system for reducing latency associated with cache coherence directory misses on external caches in a shared distributed memory data processing system, comprising:
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a cache coherence directory;
a directory cache;
first caching logic for evaluating said cache coherence directory for possible prefetching of a directory entry into said directory cache;
second caching logic for setting a prefetch miss indicator in response to said prefetch evaluation resulting in a directory miss;
first protocol logic for consulting said prefetch miss indicator during subsequent processing of a memory request corresponding to said directory entry; and
second protocol logic for taking an accelerated snoop response action based on said prefetch miss indicator being set. - View Dependent Claims (12, 13, 14, 18, 19, 20)
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- 15. A system in accordance with claim 111 further including a prefetch miss buffer and wherein said second caching logic includes logic for storing a tag for said directory entry in a prefetch miss buffer.
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21. A data processing node adapted for network interconnection in a shared distributed memory data processing system, comprising:
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a plurality of processors;
a plurality of caches respectively associated with said processors;
a node main memory;
a coherence controller;
a bus interconnecting said caches, said main memory and said coherence controller;
a cache coherence directory for locating cached copies of local memory blocks in external nodes of said data processing system;
a directory cache for temporarily storing directory entries from said cache coherence directory;
first caching logic in said coherence controller for evaluating said cache coherence directory for possible prefetching of a directory entry into said directory cache;
second caching logic in said coherence controller for setting a prefetch miss indicator as a result of said prefetch evaluation resulting in a directory miss signifying that there are no external cached copies of a memory block associated with said directory entry;
first protocol logic for consulting said prefetch miss indicator during subsequent processing of a memory block request corresponding to said directory entry; and
second protocol logic for taking an accelerated snoop response action based on said prefetch miss indicator being set;
whereby latency associated with said directory miss is reduced by virtue of said accelerated response.
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22. An article of manufacture for reducing latency associated with cache coherence directory misses on external caches in a shared distributed memory data processing system, comprising:
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one or more data storage media;
means recorded on said data storage media for programming a device to operate as by;
evaluating a cache coherence directory for possible prefetching of a directory entry into a directory cache;
setting a prefetch miss indicator in response to said prefetch evaluation resulting in a directory miss;
consulting said prefetch miss indicator during subsequent processing of a memory request corresponding to said directory entry; and
taking an accelerated snoop response action based on said prefetch miss indicator being set. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification