Method and apparatus for hardware packets reassembly in constrained networks

• US 20060106946A1
• Filed: 07/05/2005
• Published: 05/18/2006
• Est. Priority Date: 10/29/2004
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Agarwal, Puneet, Cheok, Yook-Khai
• Granted Patent: US 7,991,007 B2
• Time in Patent Office: Days
• US Class Current: 709/250
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation

Abstract

A hardware packets reassembly apparatus and method includes an ingress unit receiving and parsing a data packet, recognizing fragments corresponding to the data packet, and outputting control information of the fragments. An en-queue unit stores the control information of each fragment, links each related fragment based on the control information, and enqueues the data packet when all fragments are available corresponding to the data packet, wherein the data packet is enqueued only when all of the fragments corresponding to the data packet are available in a sequential order. A dequeue unit dequeues the data packet from a packet descriptor, and scheduling the data packet based on a corresponding class of service. An egress unit assembles all fragments corresponding to the data packet into a full packet and outputting the assembled data packet from an output port.

Claims

1. A hardware packets reassembly apparatus, comprising:

an ingress unit receiving and parsing a data packet, recognizing fragments corresponding to the data packet, and outputting control information of the fragments;

an en-queue unit storing the control information of each fragment, linking each related fragment based on the control information, and enqueuing the data packet when all fragments are available corresponding to the data packet, wherein the data packet is enqueued only when all of the fragments corresponding to the data packet are available in a sequential order;

a dequeue unit dequeuing the data packet from a packet descriptor, and scheduling the data packet based on a corresponding class of service; and

an egress unit assembling all fragments corresponding to the data packet into a full packet and outputting the assembled data packet from an output port.

2. The hardware packets reassembly apparatus as recited in claim 1, wherein the control information comprises at least one of source and destination address, fragment payload size, fragment identity, fragment payload offset, source and destination ports, class of service of the data packet, and a tunnel key.

3. The hardware packets reassembly apparatus as recited in claim 1, wherein, using the control information, the ingress unit identifies whether a fragment is received.

4. The hardware packets reassembly apparatus as recited in claim 1, wherein, when the ingress unit identifies that the fragment is received, the ingress unit detects, in a hardware platform, a sequence number of the fragment corresponding to the data packet with respect to other fragments based on a fragment identification and offset.

5. The hardware packets reassembly apparatus as recited in claim 1, wherein the ingress unit determines the control information related to a forwarding decision for the data packet and the en-queue unit.

6. The hardware packets reassembly apparatus as recited in claim 1, wherein the en-queue unit further comprises a fragment link buffer and the en-queue unit and de-queue stage share a packet memory buffer and a packet descriptor, wherein each control information of each fragment from the ingress unit is maintained and stored in the fragment link buffer before enqueuing the data packet, while a payload is stored in the packet memory buffer.

7. The hardware packets reassembly apparatus as recited in claim 6, wherein wherein the fragment link buffer checks an order of the fragments received, checks for missing fragments, and aging of the fragments in the fragment link buffer.

8. The hardware packets reassembly apparatus as recited in claim 7, wherein wherein the fragment link buffer comprises a link buffer CAM and link buffer RAM, and the fragment link buffer compares a field of an incoming fragment with existing content inside the link buffer CAM.

9. The hardware packets reassembly apparatus as recited in claim 8, wherein when the comparison is a miss, a fragment offset is zero, and the link buffer is not full, the fragment link buffer creates a new entry insertion of the incoming fragment, wherein an entry is allocated to store the source port/address and the fragment ID, a valid bit of the entry is turned on, and an aging counter is turned on.

10. The hardware packets reassembly apparatus as recited in claim 8, wherein when the comparison is a miss, a fragment offset is non-zero, the fragment is dropped, the payload corresponding with the fragment is not stored, and the link buffer RAM is not updated.

11. The hardware packets reassembly apparatus as recited in claim 8, wherein when the comparison is a hit and a fragment offset is zero, the fragment link buffer determines that there is an older first fragment in the link buffer.

12. The hardware packets reassembly apparatus as recited in claim 8, wherein when the comparison is a hit and a fragment offset is non-zero, the fragment is dropped, the payload corresponding with the fragment is stored as a second fragment, and the link buffer RAM is not updated.

13. The hardware packets reassembly apparatus as recited in claim 8, wherein when the comparison is a hit and the fragment offset is non-zero, the fragments are determined to be received in order and configured to be reassembled.

14. The hardware packets reassembly apparatus as recited in claim 8, further comprising:

an aging counter counting a time period from when the fragment is received to a threshold level where the link buffer entry corresponding to the fragment is aged and invalidated and the counter resets itself for a next insertion of the link buffer entry.

15. The hardware packets reassembly apparatus as recited in claim 1, wherein the de-queue unit comprises a scheduler selecting and scheduling output of the linked shim headers and first and second fragments to the egress unit.

16. The hardware packets reassembly apparatus as recited in claim 1, wherein the ingress unit parses the data packet into at least two fragments.

17. The hardware packets reassembly apparatus as recited in claim 16, wherein the egress unit assembles the fragments by adding additional fields to a Packet Link RAM to store context for more than one fragment.

18. The hardware packets reassembly apparatus as recited in claim 1, wherein the ingress unit parses the data packet into more than two fragments, where a number of fragments is determined from the packet header.

19. The hardware packets reassembly apparatus as recited in claim 18, wherein the egress unit assembles the fragments by adding additional fields to a Packet Link RAM to store context for more than one fragment.

20. A hardware packets reassembly method, comprising:

receiving and parsing a data packet, recognizing fragments corresponding to the data packet, and outputting control information of the fragments;

storing the control information of each fragment;

linking each related fragment based on the control information;

enqueuing the data packet when all fragments are available corresponding to the data packet, wherein the data packet is enqueued only when all of the fragments corresponding to the data packet are available in a sequential order;

dequeuing the data packet from a packet descriptor, and scheduling the data packet based on a corresponding class of service; and

assembling all fragments corresponding to the data packet into a full packet and outputting the assembled data packet from an output port.

21. A hardware packets reassembly apparatus, comprising:

means for receiving and parsing a data packet, recognizing fragments corresponding to the data packet, and outputting control information of the fragments;

means for storing the control information of each fragment, linking each related fragment based on the control information, and enqueuing the data packet when all fragments are available corresponding to the data packet, wherein the data packet is enqueued only when all of the fragments corresponding to the data packet are available in a sequential order;

means for dequeuing the data packet from a packet descriptor, and scheduling the data packet based on a corresponding class of service; and

means for assembling all fragments corresponding to the data packet into a full packet and outputting the assembled data packet from an output port.