Cyclic flash memory wear leveling

• US 20060106972A1
• Filed: 11/15/2004
• Published: 05/18/2006
• Est. Priority Date: 11/15/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Sinclair, Alan W., Smith, Peter J., Gorobets, Sergey A., Bennett, Alan D., Royall, Philip D.
• Granted Patent: US 7,441,067 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated in a manner to level out the wear of the individual blocks through repetitive erasing and re-programming. This may be accomplished without use of counts of the number of times the individual blocks experience erase and re-programming but such counts can optionally aid in carrying out the wear leveling process. Individual active physical blocks are chosen to be exchanged with those of an erased block pool in a predefined order.

Claims

1. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a minimum number of memory cells that are simultaneously erasable and wherein incoming blocks of data assigned logical block addresses are programmed into those of the plurality of physical blocks maintained as an erased block pool, comprising:

identifying at least one of the plurality of physical blocks at a time other than those in the erased block pool for a wear leveling exchange by cycling through addresses of blocks in a characterized order, and

exchanging the identified at least one of the plurality of physical blocks with a corresponding number of one or more physical blocks within the erased block pool.

2. The method of claim 1, wherein identifying at least one of the plurality of physical blocks at a time includes cycling through addresses of the blocks in a predefined sequence.

3. The method of claim 1, wherein identifying at least one of the plurality of physical blocks at a time includes cycling through addresses of the blocks in a random order.

4. The method of claim 1, wherein identifying at least one of the plurality of physical blocks at a time includes cycling through addresses of the blocks in a pseudo-random order.

5. The method of claim 1, wherein exchanging the identified blocks includes copying data from the identified at least one of the plurality of physical blocks into said corresponding number of physical blocks within the erased block pool, and updating a mapping of at least one logical block address from said at least one of the plurality of physical blocks to said corresponding number of one or more physical blocks within the erased block pool.

6. The method of claim 5, additionally comprising, after copying the data, erasing the identified at least one of the plurality of physical blocks and placing the erased at least one block into the erase pool.

7. The method of claim 6, wherein those of the plurality of physical blocks maintained as an erased block pool are less than five per-cent of a total number of the plurality of physical blocks.

8. The method of claim 5, wherein copying data includes copying data from the identified at least one of the plurality of physical blocks in stages of less than all of said data at a time.

9. The method of claim 1, wherein identifying at least one of the plurality of physical blocks for a wear leveling exchange is accomplished without reference to a number of erase cycles experienced by the individual physical blocks.

10. The method of claim 1, wherein identifying at least one of the plurality of physical blocks at a time includes doing so at intervals of a predetermined number of the plurality of physical blocks within the erased block pool being programmed with data.

11. The method of claim 1, wherein cycling through addresses of blocks in a characterized order includes cycling through physical addresses of the plurality of physical blocks.

12. The method of claim 1, wherein cycling through addresses of blocks in a characterized order includes cycling through logical addresses of blocks of data stored in the memory.

13. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a minimum number of memory cells that are simultaneously erasable and wherein incoming data are programmed into those of the plurality of physical blocks maintained as an erased block pool, comprising:

identifying at least one of the plurality of physical blocks at a time other than those in the erased block pool for a wear leveling exchange by cycling through addresses of the plurality of physical blocks in a predefined order,

monitoring an operational parameter associated with programming data into those of the plurality of physical blocks maintained as an erased block pool, and

in response to the monitored operational parameter reaching a preset threshold, exchanging the identified at least one of the plurality of physical blocks with a corresponding number of at least one of the physical blocks within the erased block pool.

14. The method of claim 13, wherein monitoring the operational parameter includes monitoring an operational parameter other than an indication of the number of erase cycles experienced by individual ones of the plurality of physical blocks.

15. The method of claim 14, wherein identifying at least one of the plurality of physical blocks at a time is accomplished without reference to an indication of the number of erase cycles experienced by individual ones of the plurality of physical blocks.

16. The method of claim 13, wherein monitoring the operational parameter includes monitoring a number of one or more times that erased pool blocks have been programmed with data since a previous wear leveling exchange.

17. The method of claim 16, wherein the preset threshold is a number of times blocks from the erased pool have been programmed with data.

18. The method of claim 16, which additionally comprises maintaining within the system indications of a number of erase cycles individually experienced by the plurality of physical blocks, and wherein monitoring the operational parameter includes monitoring a number of erase cycles experienced by the erased pool blocks relative to a number of erase cycles experienced by the plurality of physical blocks, the preset threshold being a difference between the number of erase cycles experienced by the erased pool blocks and the plurality of physical blocks.

19. The method of claim 18, wherein monitoring the number of erase cycles experienced by the erased pool blocks is carried out relative to an average of a number of erase cycles experienced by the plurality of physical blocks.

20. The method of claim 16, which additionally comprises maintaining within the system indications of a number of erase cycles individually experienced by the plurality of physical blocks, and wherein identifying at least one of the plurality of physical blocks at a time for a wear leveling exchange includes selecting one of a sub-set of the plurality of physical blocks having an indication of a lower number of erase cycles than other physical blocks within the sub-set of physical blocks.

21. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a minimum number of memory cells that are simultaneously erasable and wherein incoming blocks of data have logical block addresses mapped into corresponding physical blocks, comprising:

identifying at least one of the plurality of physical blocks at a time other than those in the erased block pool for a wear leveling exchange by cycling through the logical block addresses in a predefined order, and

exchanging an identified at least one of the plurality of physical blocks with a corresponding number of at least one other of the physical blocks.

22. The method of claim 21, wherein the exchange is accomplished without reference to a number of operational cycles experienced by the blocks.

23. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a minimum number of memory cells that are simultaneously erasable, comprising:

mapping a range of logical block addresses into addresses of a proportion of the plurality of physical blocks that leaves an additional number of physical blocks providing an erased block pool,

in response to requests to store data in at least one of the range of logical block addresses, converting said at least one logical block address into an address of at least one physical block residing in the erased block pool and then writing the data into said at least one physical block of the erased block pool,

identifying one of the plurality of physical blocks for a wear leveling exchange,

after a given number of memory programming operations, exchanging the identified one of the plurality of physical blocks with one of the number of physical blocks residing in the erased block pool, and

repeating identifying and exchanging with others of the plurality of physical blocks in a predefined order.

24. The method of claim 23, wherein said given number of memory programming operations include a number of one or more times that one of the physical blocks of the erase pool are programmed.

25. The method of claim 23, wherein identifying physical blocks includes determining whether the identified physical block is within the erase block pool or subject to a pending programming operation, in either case the identified physical block is not exchanged.

26. The method of claim 23, wherein exchanging the identified blocks includes copying data from the identified one of the plurality of physical blocks into said corresponding number of physical blocks within the erased block pool, and changing mapping of at least one logical block address from said at least one of the plurality of physical blocks to said corresponding number of one or more physical blocks within the erased block pool.