Bit line structure and method for the production thereof

• US 20060108692A1
• Filed: 11/14/2005
• Published: 05/25/2006
• Est. Priority Date: 05/14/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tempel, Georg, Kakoschke, Ronald, Schuler, Franz
• Granted Patent: US 7,687,842 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.

Claims

1. A bit line structure comprising

a substrate containing a trench;

a first trench insulating layer disposed at a surface of the trench;

a first trench filling layer disposed at a surface of the first trench insulating layer and which fills a lower section of the trench;

a second trench insulating layer disposed on a surface of the first trench filling layer;

a second electrically conductive trench filling layer forming a buried bit line which is at least partly formed at a surface of the second trench insulating layer and fills an upper section of the trench up to a surface of the substrate;

first and second doping regions of a first conduction type, which are disposed in the substrate;

a first electrically conductive connection layer that electrically connects the first doping region to the second trench filling layer at surfaces of the first doping region, the first trench insulating layer, and the second trench filling layer;

a surface dielectric disposed at the surface of the substrate and the filled trench;

a surface bit line disposed at a surface of the surface dielectric; and

a second connection layer in the surface dielectric, the second connection layer connecting the surface bit line to the second doping region.

2. The bit line structure of claim 1, wherein the second trench filling layer is disposed in the upper section of the trench at a side most proximate to the first doping region, and the opposing side of the trench is filled with a third trench insulating layer.

3. The bit line structure of claims 1, wherein:

the surface dielectric comprises a first and a second dielectric layer, and

the first connection layer is disposed as a dummy contact only in the first dielectric layer.

4. The bit line structure of claim 1, wherein:

the substrate comprises a first well of a second conduction type,

the trench projects beyond the first well, and

the second trench insulating layer lies at a level between the substrate surface and an underside of the first well.

5. The bit line structure of claim 4, wherein the substrate comprises a second well of the first conduction type, in which the first well is disposed, and the trench projects beyond the second well.

8. The bit line structure of claims 1, wherein:

the surface dielectric comprises a first and a second dielectric layer, and

the first connection layer is disposed as a dummy contact only in the first dielectric layer.

10. The bit line structure of claim 1, wherein:

the substrate comprises a first well,

the trench projects beyond the first well, and

the second trench insulating layer extends between a surface of the substrate and an underside of the first well.

11. The bit line structure of claim 10, wherein the substrate comprises a second well in which the first well is disposed and the trench projects beyond the second well.

6. A bit line structure comprising

a substrate having first and second doping regions disposed therein and a trench;

a first trench insulating layer disposed in the trench;

a first trench filling layer on the first trench insulating layer;

a second trench insulating layer on the first trench filling layer;

a second trench filling layer on the second trench insulating layer;

a first electrically conductive connection layer that electrically connects the first doping region to the second trench filling layer;

a surface dielectric on the substrate and the filled trench;

a surface bit line on the surface dielectric; and

a second connection layer in the surface dielectric, the second connection layer connecting the surface bit line to the second doping region,

wherein the first and second doping regions are source and drain regions of a non-volatile semiconductor memory cell containing, as a word line stack, a first insulating layer, a charge-storing layer, a second insulating layer, and a control layer.

7. The bit line structure of claim 6, wherein the second trench filling layer is disposed in the trench at a side most proximate to the first doping region, and the opposing side of the trench is filled with a third trench insulating layer.

12. A fabrication method for a bit line structure, the method comprising:

preparing a substrate;

forming a trench in the substrate;

forming a first trench insulating layer at a surface of the trench;

forming a first trench filling layer at a surface of the trench insulating layer in a lower section of the trench;

forming a second trench insulating layer on a surface of the first trench filling layer;

forming a second electrically conductive trench filling layer as a buried bit line at a surface of the second trench insulating layer, which fills an upper section of the trench up to a surface of the substrate;

forming a word line stack at the substrate surface;

forming first and second doping regions in the substrate;

forming a first electrically conductive connection layer that electrically connects the first doping region to the second trench filling layer;

forming a surface dielectric at the substrate surface;

forming a second electrically conductive connection layer in the surface dielectric; and

forming a surface bit line at a surface of the surface dielectric such that the surface bit line contacts the second connection layer.

13. The method of claim 12, further comprising removing the second trench filling layer in the upper section of the trench on one side as far as the second trench insulating layer and filling in the removed portion with a third trench insulating layer.

14. The method of claim 12, wherein forming the surface dielectric comprises forming first and second dielectric layers, and wherein the first connection layer is formed as a dummy contact only in the first dielectric layer.

15. The method of claim 12, further comprising forming a first well of a second conduction type in the substrate, wherein:

the trench projects beyond the first well, and

the second trench insulating layer is disposed between the substrate surface and the first well.

16. The method of claim 15, further comprising forming a second well of the first conduction type in the substrate in which the first well is situated, the trench projecting beyond the second well.

17. A fabrication method for a bit line structure, the method comprising:

forming a trench in a substrate;

depositing a first trench insulating layer in the trench;

depositing a first trench filling layer on the trench insulating layer;

depositing a second trench insulating layer on the first trench filling layer;

filling a remainder of the trench, in which the second trench insulating layer has been deposited, with a second electrically conductive trench filling layer;

depositing a word line stack on the substrate after filling the trench;

forming first and second doping regions in the substrate;

connecting the first doping region to the second trench filling layer through a first electrically conductive connection layer;

depositing a surface dielectric on the substrate after depositing the first electrically conductive connection layer;

depositing a second electrically conductive connection layer in the surface dielectric; and

forming a surface bit line on the surface dielectric such that the surface bit line contacts the second connection layer.

18. The method of claim 17, further comprising removing a portion of the second trench filling layer and filling in the removed portion with a third trench insulating layer such that the second trench filling layer and third trench insulating layer are disposed in parallel.

19. The method of claim 17, wherein depositing the surface dielectric comprises depositing first and second dielectric layers, the first connection layer formed as a dummy contact only in the first dielectric layer.

20. The method of claim 17, further comprising forming a first well in the substrate, wherein:

the trench projects beyond the first well, and

the second trench insulating layer is formed between a surface of the substrate and the first well.

21. The method of claim 20, further comprising forming a second well in the substrate in which the first well is situated, the trench projecting beyond the second well.

22. A bit line structure comprising:

means for providing a filled trench in a substrate;

means for providing a word line stack on the substrate;

means for connecting a first doping region in the substrate to a conductive layer in the trench;

means for isolating the connecting means from external contact; and

means for electrically connecting externally to the isolated connecting means.

23. The bit line structure of claim 22, wherein:

the substrate comprises crystalline silicon,

the means for providing the filled trench comprises highly doped polysilicon, and

the means for connecting the first doping region comprises a silicide.

24. The bit line structure of claims 23, wherein:

the means for isolating the connecting means comprises multiple layers, and

the means for connecting the first doping region is disposed only in one of the multiple layers.

25. The bit line structure of claim 23, wherein the means for providing the filled trench comprises silicon dioxide.