Strained silicon fin structure
First Claim
1. A strained silicon fin structure comprising an insulator substrate:
- a silicon seed fin structure disposed on the substrate; and
a strained channel layer fabricated on the seed fin structure, the channel layer material having a lattice constant different than that of the seed fin material, whereby the channel layer strain is the result of the lattice mismatch between the channel layer material and the seed fin material.
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Abstract
Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.
253 Citations
12 Claims
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1. A strained silicon fin structure comprising
an insulator substrate: -
a silicon seed fin structure disposed on the substrate; and
a strained channel layer fabricated on the seed fin structure, the channel layer material having a lattice constant different than that of the seed fin material, whereby the channel layer strain is the result of the lattice mismatch between the channel layer material and the seed fin material. - View Dependent Claims (2, 3)
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4. A strained silicon finFET device comprising
an insulator substrate; -
A source and a drain sandwiching a strained channel region disposing on the substrate, the strained channel comprising a gate dielectric layer disposed on the strained channel; and
a gate over the strained channel and electrically isolated therefrom by the gate dielectric. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11)
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12-30. -30. (canceled)
Specification